Analog Devices ADRV9001, User Manual

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Preliminary Technical Data UG-1828
Rev. PrC | Page 319 of 338
• Assert/Deassert entries are frame locations, they are not durations, for example if RX1 primary assert is 0 and primary deassert
is 10000 μs, this means within the specified frame the RX1 enable is on from 0 to 10000 μs and off for the rest of the frame.
• In Figure 306, it shows visually what primary/secondary assert/deassert mean. Black and grey indicates TX and RX subframe
data.
• Signal Input
•
User can change the values of a signal already in the table or add a new signal to the table. This is done by selecting the row to be
edited in the table, filling in the parameters in the row underneath the table and clicking Apply.
• To add a new row, select the blank row at the bottom of the table and click Apply with the parameters for the new row.
Figure 306. TDD Frame Timing Illustration
Table 114. TDD Signals
Signal Description
RX1 Pin
TX1 Pin
RX2 Pin
TX2 Pin These signals are hardwired to the Rx/Tx ENABLE pins (used as
SETUP signals in FH)
ORX1 Pin
ORX2 Pin This can be used as ORX enable signal when routed to the GPIO
assigned as ORX control
RX1 DMA
RX2 DMA
TX1 DMA
TX2 DMA
ORX1 DMA
ORX2 DMA The DMA enables that gate data transfer for each of the channels
RX1 DMA Trigger
RX2 DMA Trigger
TX1 DMA Trigger
TX2 DMA Trigger
ORX1 DMA Trigger
ORX2 DMA Trigger These signals can be configured as triggers for the DMAs to signify
that data transfer on that channel should only occur when the
trigger signal has pulsed high followed by the DMA signal for that
channel going high.
SMA1 Trigger Hardwired to dedicated SMA (J67) on the ZC706 board, this signal
can be used to trigger external equipment. No option on ZCU102
currently.
SMA2 Trigger Hardwired to dedicated SMA (J68) on the ZC706 board, this signal
can be used to trigger external equipment. No option on ZCU102
currently.
General Purpose 1/ Hop Pin General Purpose signal that can be routed to GPIO pins. This is also
used as the Hop Pin in FH mode.
General Purpose 2 - 6 General purpose signals that can be routed to GPIO pins as needed
PRIMARY DEASSERT TIME
PRIMARY ASSERT TIME
PRIMARY DEASSERT TIME
PRIMARY ASSERT TIME
SECONDARY DEASSERT TIME
SECONDARY DEASSERT TIME
SECONDARY DEASSERT TIME
SECONDARY ASSERT TIME
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