Preliminary Technical Data
UG-1828
Rev. PrC | Page 47 of 338
SERIAL PERIPHERAL INTERFACE (SPI)
The SPI bus provides the mechanism for digital control by a baseband processor. Each SPI register is 8 bits wide, and each register
contains control bits, status monitors, or other settings that control all functions of the device. This section is mainly an information-only
section meant to give the user an understanding of the hardware interface used by the baseband processor to control the device. All
control functions are implemented using the API detailed within this document. The following sections explain the specifics of this
interface.
SPI CONFIGURATION
Users can configure SPI settings for the device with different SPI controller configurations by configuring member values of the
adi_adrv9001_SpiSettings_t data structure. The adi_adrv9001_SpiSettings_t data structure contains:
typedef struct adi_adrv9001SpiSettings
{
uint8_t msbFirst;
uint8_t enSpiStreaming;
uint8_t autoIncAddrUp;
uint8_t fourWireMode;
adi_adrv9001_CmosPadDrvStr_e cmosPadDrvStrength;
} adi_adrv9001_SpiSettings_t;
The parameters for this structure are listed in Table 12.
Table 12. SPI Settings Data Structure
Structure Member
Value
Function
Default
MSBFirst
0x00
Least significant bit first.
0x01
0x01
Most significant bit first.
enSpiStreaming
0x00
Disable SW feature. Section Multi-Byte Data Transfer (SPI
Streaming) describes this mode of operation.
0x00
0x01
Enable SW feature to improve SPI throughput. Section Multi-
Byte Data Transfer (SPI Streaming) describes this mode of
operation.
Not Recommended since most registers in ADRV9001 API
are not consecutive.
autoIncAddrUp
0x00
Auto-decrement. Functionality intended to be used with SPI
Streaming.
Sets address auto-decrement -> next addr = addr -1
0x01
0x01
Auto-increment. Functionality intended to be used with SPI
Streaming.
Sets address auto-increment -> next addr = addr +1
fourWireMode
0x00
SPI hardware implementation. Use 3-wire SPI (SDIO pin is
bidirectional). Figure 23 shows example of SPI 3-wire mode
of operation.
NOTE: ADI's FPGA platform always uses 4-wire mode.
0x01
0x01
SPI hardware implementation. Use 4-wire SPI. Figure 21 and
Figure 22 show examples of SPI 4 –wire mode of operation.
NOTE: Default mode for ADI's FPGA platform is 4-wire mode.
cmosPadDrvStrength
0x00
5 pF load @ 75 MHz
0x01
0x01
100 pF load @ 20 MHz
Any value that is not listed in the table is invalid.
For more details, refer to ADRV9001_API doxygen file provided in ADRV9001 SDK package.
