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13.3.2
Technical data
Table 327:
Configurable logic blocks
Logic block
Quantity
with cycle
time
Range or value
Accuracy
5 ms
20 ms
100 ms
AND
60
60
160
-
-
OR
60
60
160
-
-
XOR
10
10
20
-
-
INVERTER
30
30
80
-
-
SRMEMORY
10
10
20
-
-
RSMEMORY
10
10
20
-
-
GATE
10
10
20
-
-
PULSETIMER
10
10
20
(0.000–
90000.000) s
± 0.5% ± 25 ms for 20
ms cycle time
TIMERSET
10
10
20
(0.000–
90000.000) s
± 0.5% ± 25 ms for 20
ms cycle time
LOOPDELAY
10
10
20
Table 328:
Configurable logic Q/T
Logic block
Quantity with
cycle time
Range or value
Accuracy
20 ms
100 ms
ANDQT
20
100
-
-
ORQT
20
100
-
-
XORQT
10
30
-
-
INVERTERQT
20
100
-
-
RSMEMORYQT
10
30
-
-
SRMEMORYQT
15
10
-
-
PULSETIMERQT
10
30
(0.000–
90000.000) s
± 0.5% ± 25 ms for 20 ms
cycle time
TIMERSETQT
10
30
(0.000–
90000.000) s
± 0.5% ± 25 ms for 20 ms
cycle time
INVALIDQT
6
6
-
-
INDCOMBSPQT
10
10
-
-
INDEXTSPQT
10
10
-
-
1MRK 502 048-UUS A
Section 13
Logic
487
Technical manual
Summary of Contents for 650 series
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