Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
271
UG586 November 30, 2016
Chapter 1:
DDR3 and DDR2 SDRAM Memory Interface Solution
win_byte_select
can be used to select between each byte groups measured results and
display them to the Vivado logic analyzer feature waveform window. To calculate the total
data valid window use the following equation:
(Total # of taps × CLK_PERIOD)/128 = Total Valid Data Window
Note:
The Read window measurement results are stored in a block RAM after
win_start
is
asserted.
Manual Window Check
To manually measure the data window margin, follow these steps:
1. Enable the manual window check by asserting
dbg_sel_pi_incdec
.
Note:
When
dbg_sel_pi_incdec
is enabled,
dbg_pi_counter_read_cal
does not represent
the true centered PHASER_IN tap value.
2. Set the ILA trigger to cmp_error = 1.
3. Manually increment/decrement the taps using the
dbg_pi_f_inc
or
dbg_pi_f_dec
an event is triggered indicating a left or right edge was found. Note the number of taps
that occurred until event triggered.
4. Manually increment/decrement the taps back the same # of taps.
5. Issue a single pulse event to
dbg_clear_error
, and reset the ILA trigger.
6. Manually increment/decrement the taps in the other direction using the
dbg_pi_f_inc
or
dbg_pi_f_dec
an event is triggered indicating a left or right edge
was found. Note the number of taps that occurred until event triggered.
7. Add up the left and right tap values determined and calculate the total data valid
window using the following equation:
(Total # of taps × CLK_PERIOD)/128 = Total Valid Data Window
Analyzing Calibration Results
When data errors occur, the results of calibration should be analyzed to ensure the results
are expected and accurate. Each of the above debugging calibration sections notes what
the expected results are such as how many edges should be found, how much variance
across byte groups should exist, and others. Follow these sections to capture and then
analyze the calibration results.