Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
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UG586 November 30, 2016
Chapter 3:
RLDRAM II and RLDRAM 3 Memory Interface Solutions
Read Path
The read path includes data capture using the memory-provided read clocks and also
ensures that the read clock is centered within the data window for good margin during data
capture. Before any read can take place, calibration must occur. Calibration is the main
function of the read path and needs to be performed before the user interface can start
transactions to the memory.
Data Capture
shows a high-level block diagram of the path the read clock and the read data
captures from entering the FPGA until it is given to you. The read clock bypasses the ILOGIC
and is routed through PHASERs within each byte group. For RLDRAM II, the multiregion
BUFMR is used to get the read capture clock to the necessary PHASERS used in read data
capture. The BUFMR output can drive the PHASEREFCLK inputs of the PHASERs in the
immediate bank and also the PHASERs available in the bank above and below the current
bank. The BUFMR is needed for RLDRAM II because there can potentially be a single capture
clock for two bytes of data, and only the BUFMR can allocate the clock to the multiple
PHASERs as required.
Because RLDRAM 3 includes a capture clock per byte of data, the multiregion BUFMR is not
required. The PHASER generated byte group clocks (ICLK and ICLKDIV) are then used to
capture the read data (DQ) available within the byte group using the ISERDES block. The
calibration logic makes use of the fine delay increments available through the PHASER to
ensure the byte group clock, ICLK, is centered inside the read data window, ensuring
maximum data capture margin.
IN_FIFOs available in each byte group (shown in
) receive 4-bit data from each
DQ bit captured in the ISERDES in a given byte group and write them into the storage array.
The half-frequency PHASER_IN generated byte group clock, ICLKDIV, that captures the data
in the ISERDES is also used to write the captured read data to the IN_FIFO. The write enables
to the IN_FIFO are always asserted to enable input data to be continuously written.
For RLDRAM 3, the IN_FIFO also transfers the data from the ICLKDIV domain (which runs at
half the memory clock frequency) to the FPGA logic clock domain (which runs at a quarter
the memory clock frequency). A shallow, synchronous post_fifo is used at the receiving side
of the IN_FIFO to enable captured data to be read out continuously from the FPGA logic, in
an event of a flag assertion in the IN_FIFO which might potentially stall the flow of data from
the IN_FIFO. Calibration also ensures that the read data is aligned to the rising edge of the
FPGA logic half-frequency clock and that read data from all the byte groups have the same
delay. More details about the actual calibration and alignment logic is explained in the
section.