Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
569
UG586 November 30, 2016
Chapter 4:
LPDDR2 SDRAM Memory Interface Solution
Simulation Flow Using Vivado Simulator
1. In the
Open IP Example Design
Vivado project, under
Flow Navigator
, select
Simulation Settings
(
2. Under the
Simulation
tab as shown in
, set the
xsim.simulate.runtime
as 1 ms (there are simulation RTL directives which stop the simulation after a certain
period of time, which is less than 1 ms). Apply the settings and select
OK
.
X-Ref Target - Figure 4-39
Figure 4-39:
Simulation with Vivado Simulator