Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
349
UG586 November 30, 2016
Chapter 2:
QDR II+ Memory Interface Solution
°
The above settings must ensure the minimum PLL VCO frequency (FVCOMIN) is
met. For specifications, see the appropriate DC and Switching Characteristics Data
Sheet. The
7 Series FPGAs Clocking Resources User Guide
(UG472)
includes
the equation for calculating FVCO.
°
The relationship between the input period and the memory period is InputPeriod =
(MemoryPeriod × M)/(D × D1).
• The clock input (
sys_clk
) can be input on any CCIO in the column where the memory
interface is located; this includes CCIO in banks that do not contain the memory
interface, but must be in the same column as the memory interface. The PLL must be
located in the bank containing the clock sent to the memory. To route the input clock
to the memory interface PLL, the CMT backbone must be used. With the MIG
implementation, one spare interconnect on the backbone is available that can be used
for this purpose.
°
MIG versions 1.4 and later allow this input clocking setup and properly drive the
CMT backbone.
°
CLOCK_DEDICATED_ROUTE = BACKBONE constraint is used to implement CMT
backbone, following warning message is expected. It can be ignored safely.
WARNING: [Place 30-172] Sub-optimal placement for a clock-capable IO pin and PLL
pair. The flow will continue as the CLOCK_DEDICATED_ROUTE constraint is set to
BACKBONE.
u_mig_7series_0/c0_u_clk_ibuf/diff_input_clk.u_ibufg_sys_clk (IBUFDS.O) is locked
to IOB_X0Y176
u_mig_7series_0/c0_u_infrastructure/plle2_i (PLLE2_ADV.CLKIN1) is locked to
PLLE2_ADV_X0Y1
u_mig_7series_0/c1_u_infrastructure/plle2_i (PLLE2_ADV.CLKIN1) is locked to
PLLE2_ADV_X0Y5
......
• For QDR II+ SRAM interfaces that have the memory system input clock (
sys_clk
)
placed on CCIO pins within one of the memory banks, MIG assigns the DIFF_HSTL_I I/O
standard (VCCO = 1.5V) to the CCIO pins. Because the same differential input receiver is
used for both DIFF_HSTL_I and LVDS inputs, an LVDS clock source can be connected
directly to the DIFF_HSTL_I CCIO pins.
• It is acceptable to have differential inputs such as LVDS and LVDS_25 in I/O banks that
are powered at voltage levels other than the nominal voltages required for the outputs
of those standards (1.8V for LVDS outputs, and 2.5V for LVDS_25 outputs). However,
these criteria must be met:
a. The optional internal differential termination is not used (DIFF_TERM = FALSE, which
is the default value).
Note:
This might require manually changing DIFF_TERM parameter located in the top-level
module or setting this in the UCF or XDC.
b. The differential signals at the input pins meet the VIN requirements in the
Recommended Operating Conditions table of the specific device family data sheet.