TOBY-L4 series - System Integration Manual
UBX-16024839 - R04
System description
Page 16 of 143
Function
Pin Name
Pin No
I/O
Description
Remarks
I2C1
SCL1
54
O
I2C1 clock
1.8 V open drain.
External pull-up required.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDA1
55
I/O
I2C1 data
1.8 V open drain.
External pull-up required.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDIO
SDIO_D0
66
I/O
SDIO serial data [0]
SDIO interface for communication with Wi-Fi / Bluetooth.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDIO_D1
68
I/O
SDIO serial data [1]
SDIO interface for communication with Wi-Fi / Bluetooth.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDIO_D2
63
I/O
SDIO serial data [2]
SDIO interface for communication with Wi-Fi / Bluetooth.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDIO_D3
67
I/O
SDIO serial data [3]
SDIO interface for communication with Wi-Fi / Bluetooth.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDIO_CLK
64
O
SDIO serial clock
SDIO interface for communication with Wi-Fi / Bluetooth.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDIO_CMD
65
I/O
SDIO command
SDIO interface for communication with Wi-Fi / Bluetooth.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
Ethernet
V_ETH
221
O
Ethernet Interface
supply output
Ethernet (RGMII / RMII) interface supply output.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_TX_CLK
29
O
Ethernet
Transmission Clock
RGMII: Transmit reference clock (TXC).
RMII: Reference clock (REF_CLK).
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_TX_CTL
33
O
Ethernet Transmit
Control
RGMII: Control signal for the transmit data (TXEN on TXC
rising edge; TXEN xor TXER on TXC falling edge).
RMII: Control signal for the transmit data (TX_EN).
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_TXD0
37
O
Ethernet Transmit
Data [0]
RGMII: Tx data bit 0 / 4 on TXC rising / falling edges.
RMII: Tx data bit 0 in sync with REF_CLK.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_TXD1
36
O
Ethernet Transmit
Data [1]
RGMII: Tx data bit 1 / 5 on TXC rising / falling edges.
RMII: Tx data bit 1 in sync with REF_CLK.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_TXD2
35
O
Ethernet Transmit
Data [2]
RGMII: Tx data bit 2 / 6 on TXC rising / falling edges.
RMII: Not used.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_TXD3
34
O
Ethernet Transmit
Data [3]
RGMII: Tx data bit 3 / 7 on TXC rising / falling edges.
RMII: Not used.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.