Themis TA64, Руководство по оборудованию

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5-17
Themis Computer
5—Field-Programmable Gate Array (FPGA)
Register Description
5.5.18 WATCHDOG_INT_MASK Register
This 8-bit WATCHDOG_INT_MASK register is used to individually enable or dis-
able interrupts from each of the watchdog timers. When a bit is set to ‘1’, the corre-
sponding interrupt is masked (disabled) and the output (if any) from that watchdog
timer will remain in the inactive state.
Disabling (masking) the interrupt from a watchdog timer has no effect on the opera-
tion of the timer itself. The watchdog timers are still totally functional, and both the
Expired bit and the associated down-counter will continue to operate.
watchdog2 expire Bit 1 RO
0 means the counter’s value is not zero
1 means the counter’s value is zero
Default = 0,
This bit can be cleared by watchdog reset.
Reserved Bit 2 - 7 RO Read as 0
Table 5-17. Watchdog_2_Status Register 0xFD00.0028 (Continued)
Field Bit Access
Description
(This register must be accessed in 8-bit mode.)
Table 5-18.
Watchdog_Int_Mask register 0xFD00.0040
Field Bit Access Description
watchdog1
run
Bit 0 RW
0 means the watchdog1’s interrupt is NOT
masked.
1 means the watchdog1’s interrupt is masked.
Default = 0
watchdog2
run
Bit 1 RW
0 means the watchdog2’s interrupt (XIR_RESET)
is NOT masked.
1 means the watchdog2’s interrupt (XIR_RESET)
is masked.
Default = 0
TBD Bit 2 RW
TBD
Default = 0
Reserved Bit 3 - 7 RO Read as 0