Texas Instruments TMS320VC5509, Справочное руководство

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Clock Generation in the Sample Rate Generator
3-5 Sample Rate Generator of the McBSP SPRU592E
3.2.1 Choosing an Input Clock
The sample rate generator must be driven by an input clock signal from one
of the four sources selectable with the SCLKME bit of PCR and the CLKSM
bit of SRGR2 (see Table 3
− 2). When CLKSM = 1, the minimum divide down
value in CLKGDV bits should be 1.
Note:
The maximum frequency for the McBSP on the TMS320VC5503/5507/5509
and TMS320VC5510 devices is 1/2 the CPU clock frequency. The maximum
frequency for the McBSP on the TMS320VC5501 and TMS320VC5502
devices is 1/2 the frequency of the slow peripherals clock. For more
information on programming the frequency of the slow peripheral clock, see
the TMS320VC5501 Fixed-Point Digital Signal Processor Data Manual
(literature number SPRS206) or the TMS320VC5502 Fixed-Point Digital
Signal Processor Data Manual (literature number SPRS166). Other timing
limitations may also apply. See the device-specific data manual for detailed
information on the McBSP timing requirements.
When driving CLKX or CLKR at the pin, choose an appropriate input clock
frequency. When using the internal sample rate generator for CLKX and/or
CLKR, choose an appropriate input clock frequency and divide down value
(CLKGDV).
Table 3 − 2. Choosing an Input Clock for the Sample Rate Generator With the SCLKME
and CLKSM Bits
SCLKME CLKSM
Input Clock For
Sample Rate Generator
0 0 Signal on CLKS pin
0 1 McBSP internal input clock
1 0 Signal on CLKR pin
1 1 Signal on CLKX pin