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Setting the SRG Frame-Sync Period and Pulse Width
8-27
Transmitter Configuration
SPRU592E
8.18 Setting the SRG Frame-Sync Period and Pulse Width
The FPER and FWID fields, shown in Figure 8
20, are used to set the SRG frame-sync period and pulse width.
Figure 8
−
20. Register Bits Used to Set the SRG Frame-Sync Period and Pulse Width
SRGR2
15
12 11
0
FPER
R/W-0000 0000 0000
SRGR1
15
8 7
0
FWID
R/W-0000 0000
Legend:
R = Read; W = Write; -
n
= Value after reset
Table 8
−
20. Register Bits Used to Set the SRG Frame-Sync Period and Pulse Width
Register
Bit
Name
Function
SRGR2
11-0
FPER
Sample Rate Generator Frame-Sync Period
For the frame-sync signal FSG, (FPER + 1) determines the period from the
start of a frame-sync pulse to the start of the next frame-sync pulse.
Range for (FPER + 1):
1 to 4096 CLKG cycles.
SRGR1
15-8
FWID
Sample Rate Generator Frame-Sync Pulse Width
This field plus 1 determines the width of each frame-sync pulse on FSG.
Range for (FWID + 1):
1 to 256 CLKG cycles.
8.18.1 About the Frame-Sync Period and the Frame-Sync Pulse Width
The sample rate generator can produce a clock signal, CLKG, and a
frame-sync signal, FSG. If the sample rate generator is supplying receive or
transmit frame synchronization, you must program the bit fields FPER and
FWID.
On FSG, the period from the start of a frame-sync pulse to the start of the next
pulse is (FPER + 1) CLKG cycles. The 12 bits of FPER allow a frame-sync
period of 1 to 4096 CLKG cycles, which allows up to 4096 data bits per frame.
When GSYNC = 1, FPER is a don’t care value.
Each pulse on FSG has a width of (FWID + 1) CLKG cycles. The eight bits of
FWID allow a pulse width of 1 to 256 CLKG cycles. It is recommended that
FWID be programmed to a value less than the programmed word length.
Содержание TMS320VC5509
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