Texas Instruments TMS320VC5509, Справочное руководство

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Setting the SRG Clock Divide-Down Value
7-37 Receiver Configuration SPRU592E
7.21 Setting the SRG Clock Divide-Down Value
The CLKGDV field, shown in Figure 7 − 24 and described in Table 7 − 26,
contains the SRG clock divide-down value.
Figure 7 − 24. Register Bits Used to Set the Sample Rate Generator (SRG)
Clock Divide-Down Value
SRGR1
15 8 7 0
CLKGDV
R/W-0000 0001
Legend: R = Read; W = Write; - n = Value after reset
Table 7 − 26. Register Bits Used to Set the Sample Rate Generator (SRG)
Clock Divide-Down Value
Register Bit Name Function
SRGR1 7-0 CLKGDV Sample Rate Generator Clock Divide-Down Value
The input clock of the sample rate generator is divided by ( 1) to
generate the required sample rate generator clock frequency. The default
value of CLKGDV is 1 (divide input clock by 2).
7.21.1 About the Sample Rate Generator Clock Divider
The first divider stage generates the serial data bit clock from the input clock.
This divider stage utilizes a counter, preloaded by CLKGDV, that contains the
divide ratio value.
The output of the first divider stage is the data bit clock, which is output as
CLKG and which serves as the input for the second and third stages of the
divider.
CLKG has a frequency equal to 1/( 1) times the frequency of the
sample rate generator input clock. Therefore, the sample generator input clock
frequency is divided by a value between 1 and 256. When CLKGDV is odd or
equal to 0, the CLKG duty cycle is 50%. When CLKGDV is an even value, 2p,
representing an odd divide-down, the high-state duration is p+1 cycles and the
low-state duration is p cycles.