F-8
DRAB:
See
data-read address bus (DRAB).
DRDB:
See
data read bus (DRDB).
DS:
Data memory select pin. The ’C2xx asserts DS to indicate an access to
external data memory (local or global).
DSWS:
Data-space wait-state bit(s). A value in the wait-state generator con-
trol register (WSGR) that determines the number of wait states applied
to reads from and writes to off-chip data space. On the ’C209, DSWS is
bit 1 of the WSGR; on other ’C2xx devices, DSWS is bits 8–6.
dual-access RAM:
See
DARAM.
dummy cycle:
A CPU cycle in which the CPU intentionally reloads the pro-
gram counter with the same address.
DWAB:
See
data-write address bus (DWAB).
DWEB:
See
data write bus (DWEB).
DX pin:
Serial data transmit pin. The pin on which data is transmitted serially
from the synchronous serial port; accepts a data word one bit at a time
from the transmit shift register (XSR).
E
execute phase:
The fourth phase of the pipeline; the phase in which the
instruction is executed. See also
pipeline; instruction-fetch phase;
instruction-decode phase; operand-fetch phase.
external interrupt:
A hardware interrupt triggered by an external event
sending an input through an interrupt pin.
F
FE bit:
Framing error indicator bit. Bit 10 of I/O status register (IOSR); indi-
cates whether a valid stop bit has been detected during the reception of
a character into the asynchronous serial port.
FIFO buffer:
First-in, first-out buffer. A portion of memory in which data is
stored and then retrieved in the same order in which it was stored. The
synchronous serial port has two four-word-deep FIFO buffers: one for its
transmit operation and one for its receive operation.
flash memory:
Electronically erasable and programmable, nonvolatile
(read-only) memory.
Glossary
