Tektronix 2440, Руководство пользователя

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Theory of Operation— 2440 Service
The A TRI(a and R TRIG outputs from Q287 and Q288
are TTL-buffered versions of the corresponding trigger sig­
nals and are routed to rear-panel BNC connectors.
Phase Locked Loop
The Phase Locked Loop circuit synthesizes the
500 M Hz clock used by the Acquisition System. It consists
of Phase/Frequency comparator U381 amplifier U580A, a
voltage-tuned tank circuit, and a divide-by-50 counter inter­
nal to Phase Clock Array U470. The tank-circuit resonant
frequency is set by the value of voltage-controlled capaci­
tors CR580 and CR582. The resulting clock is divided by
50 by the counter and is applied to the phase-frequency
detector U381 on the TENREF line. The TENREF signal is
compared to the reference clock 10 MHz, and any phase
or frequency error appears at the output of 1)381 as
variable width pulses. These pulses are integrated by
U580A to produce a dc voltage that represents the phase
difference (fast or slow) and magnitude of error between
the 10 M Hz clock and the divided down master clock. This
is the frequency-control voltage and varies the capacitance
of varactor diodes C R580 and CR582, part of the tank
circuit formed by the circuit board delay line, CR580 and
CR582. The tank is tuned by the control voltage so that
the master clock frequency is precisely 50 times the
reference frequency.
CCD Phase Clock
The CCD Phase Clock generates properly phased and
frequency-related clocks that control most of the Acquisi­
tion system. These functions include moving samples into
the CCD arrays, shifting within the arrays, jitter-correction
control, peak-detection control, and trigger-delay clock
generation. These clocks are derived from the 500 MHz
master clock generated by the internal oscillator and the
Phase Locked Loop circuit.
Two operating modes exist for the CCD arrays; FISO
(fast-in, slow-out) and Short-Pipe. The Phase Clock circuit
is set up to generate proper clocking signals for either
mode by loading data into Gate Array Control Register
U270 (diagram 5). This data is applied to U470 on the
CC0-CC4 (chip control 0-4) lines and on the PDOFF (peak
detector off) line. The PDOFF line enables/disables the
peak-detector output lines (PD1, PD1, PD2, and PD2) and
thus peak detection mode (see that description). The CC4
input controls whether the scope uses a non-Delay- or a
delayed-by-time trigger source. If Horizontal mode is B and
B Trigger Mode is B delay-by-time, is in normal (or delay
by time trigger mode. When set high, the phase clock will
choose the RTRIG signal as the trigger source for delay by
time, if set low, the phase clock will choose JTRIG as the
source. The CC0-CC3 inputs control operating mode and
clock selection as shown in Table 3-6.
FISO MODE. As explained in the CCD description, each
CCD is made up of two identical differential channels using
a serial-parallel-serial (SPS) structure. Samples are moved
into and shifted within the CCD arrays using properly
phased, overlapping clocks. Figure 3-5 shows a basic CCD
structure (see CCD description, diagram 10).
Depending on which of the four sides of the CCD is
being acquired, the corresponding sample gate ( L I , L2, L3
or L4) will go HI. This moves the present level of the input
signal into the input well of the CCD arrays. Before the
sample gate returns LO, the 01A (phase A1 register) clock
goes HI and the charge is shared by the adjacent cells
(input and 01). When the sample gate returns LO, all
charge moves to the 01 cell. The 02A clock then goes HI
and charge is distributed into both the 01 and
02
cells.
When 01 returns LO, all charge will move into the 02 cell.
When 8 samples have been acquired in the A register,
the Tl (transfer into B) clock moves all 8 samples from the
01A cells in parallel into the B register. The two phases of
the B clocks shift samples down the 8 parallel B registers
in a manner similar to that just described for the A register
but at 1/8th the rate. The TTLB1 clock (TTL-version of B
clock 01) is output to the Time Base Controller and allows
it to keep track of how many samples have been acquired
(in multiples of 32). This allows the Time Base Controller
to know when the proper number of “pretrigger” points
have been acquired and when to enable the Trigger
Logic Array.
Once enabled, the Trigger Logic Array begins counting
its predefined delay while samples continue to be acquired.
The DELCLK (delay clock) output to the Trigger Logic runs
at one-half the sample-clock rate, allowing the Trigger
Logic to complete any defined delay. When delay is done,
the JTRIG and RTRIG signals may be generated. When
the JTRIG occurs, the RAMP and RAMP signals from the
Trigger Logic start the Jitter-Correction Ramps. The
JTRIG signal to U470 causes the TL0 and TL1 (trigger
location-bits 0 and 1) bits to latch the phase (HI or LO) of
the L I and L2 clocks, defining in which quarter of the cycle
the trigger event occurred. The internal slow-ramp logic
circuitry of U470 becomes enabled and, on the next two
edges of the master clock, asserts the two pairs of
slow-ramp (SLRAMP) outputs. These outputs reverse the
charge direction of the Jitter-Correction Ramp circuits
(diagram 12) and start the Jitter-Correction Counters
(diagram 13) on opposite edges of the master clock. See
those descriptions for further information on trigger-jitter
correction.
Depending on trigger mode, the RTRIG (record trigger)
line will be asserted some time after JTRIG occurs. RTRIG
is synchronized to the B-register clock and is output to the
Time Base Controller on the SYNTRIG (synchronous
trigger) line, telling it to start counting post-trigger sam­
ples. The RTRIG also loads a register internal to U470
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