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Theory of Operation— 2440 Service
with the capacitance value, of the integration capacitor,
determines charge rate (slope) of the holdoff ramp; and
thereby, the holdoff time. Table 3-7 illustrates the holdoff
time as a function of the selected current source and
charging capacitor.
Charging current is stored on capacitor C882 when
holdoff intervals less than or equal to 10
ms
are desired.
For longer holdoff periods, capacitor C881 and C885 are
placed in parallel with C882 by turning Q782 on. Transistor
Q782 turns on when H 0 3 (holdoff select 3) is LO, turning
Q783 off. This pulls the gate of Q782 high and turns it on,
placing the parallel combination of C881 and C885 in
parallel with C882. Due to the relative capacitance ratios
(1000:1), C881 is the dominant integrating element in the
three-capacitor parallel combination.
H oldoff-R am p C om parators
Two Holdoff-Ramp Comparators, U871 and U881,
watch the holdoff ramp. Comparator U871 compares the
ramp level to the user-defined reference level while U871
compares it to a predefined “end-of-holdoff” level.
Initially, a HI on the Q output of Holdoff Logic flip-flop
U872A keeps Q781 turned on. The integration capacitors
are discharged, and all the charging current is being
shunted away from the capacitors through Q781. The
user-definable holdoff reference applied to U871 pin 2 via
R863 will always be more positive than this discharged
level, so the output of U871 applied to the Holdoff Logic
will be HI. This removes the reset from the Holdoff Logic
flip-flop U872A and enables the occurrence of a trigger
event (ATG going HI) to clock it.
When a trigger event occurs, discharge transistor Q781
turns off, allowing the selected integrating capacitors to
charge. When the charging ramp reaches the user-defined
HOREF (holdoff reference) level, the output of ramp com
parator U871 will go LO. This resets flip-flop U872A of the
Holdoff Logic which, in turn, turns Q781 back on.
The low-impedance path through Q781 discharges the
integration capacitor very rapidly. When this discharging
ramp crosses the - 4 . 6 volt level (defined by R887 and
R888), the output of U881 will go LO, resetting the Holdoff
Logic circuit. This ends the holdoff pulse and allows the
next trigger to be accepted.
Transistor Q781 remains on until the next trigger event,
at which time the cycle repeats itself. Propagation delays
through the Analog Trigger and the Record Trigger devices
ensure that the discharging ramp will always reach the
—5 V level before another trigger event can start the next
holdoff ramp.
Holdoff Logic
The Holdoff Logic initiates and controls the holdoff ramp
and produces the holdoff pulse controlling the delay
between one trigger event and the next. It starts the
holdoff ramp when a trigger event is detected, begins ramp
discharge when the user-defined HOREF level is reached,
and ends the holdoff pulse when the ramp crosses the
“end-of-holdoff” level.
Initially, the Set and Reset inputs of U872A will be HI,
allowing the flip-flop to watch the ATG (analog trigger) line
for a trigger event. While it is waiting, its Q output will be
HI, keeping Q781 on and the integration capacitors
discharged.
When an ATG occurs, the HI level at the_ input of the
flip-flop is clocked to the Q output while the Q output goes
Table 3-7
Holdoff Delays vs Current Source/Charging Capacitor Combinations
Charging
Holdoff Delay Range
Capacitor
Current Source
909
m
A
90.0
m
A
9.09
m
A
827
m
A
1000 pF
10 ns -
100 ns -
1 MS -
D
100 ns
1 MS
10 MS
E
L
10
fis
-
100
ms
-
1 ms -
10 ms -
A
1.1
fiF
100
ms
1 ms
10 ms
100 ms
Y
3-59
Содержание 2440
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