Tektronix 2440, Руководство пользователя

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Theory of Operation— 2440 Service
C alibrator
The Calibrator circuit is composed of U731, U831,
Q831, and associated components. Output frequency is
set by the CALCLK signal from the Time Base Controller
(diagram 8). The output frequency follows the SEC/DIV
setting from 50 ns/div to 20 ms/div and is set to display
from 2.5 to 10 calibrator cycles across the ten graticule
divisions over those settings. This feature allows quick and
easy verification of the acquisition time base rates. The
Calibrator circuitry is essentially a voltage regulator that is
switched off and on, producing a square-wave output sig­
nal at the CALIBRATOR loop.
When the CALCLK (calibrator clock) signal, at the base
of U831D (applied via R885) is LO, U831C (configured as
a diode) is forward biased. This shunts bias current away
from Q831, keeping it turned off. When Q831 is off, the
front-panel CALIBRATOR output is pulled to ground
potential, through R831, thereby setting the lower limit of
the CALIBRATOR square-wave signal.
As the CALCLK signal goes from LO to HI, the base of
U831D is pulled HI, reverse biasing U831C. Bias current
for Q831 now flows through R834 and R835, turning it on.
The voltage at the emitter of Q831 rises to a level of
+ 2 .4 volts, determined by the voltage regulator composed
of U 731, U831A, U831B, Q831, and associated
components. This regulated level is divided down to
+ 4 0 0 mV p-p, by the resistive divider formed by R832 on
the side board and R102 on the main board, and applied
to the front-panel CALIBRATOR loop at an effective out­
put impedance of 50 Q.
CCD OUTPUT
The CCD Output circuits (diagram 14) convert the four
differential output signals from each CCD into single-ended
signals for subsequent A/D conversion. The single-ended
analog voltages are applied to Track-and-Hold circuits
where they are held until the time-multiplexed A/D Con­
verter digitizes the stored samples.
G ain-C ell A m plifiers
There are eight identical Gain-Cell amplifiers (two on
each of four Gain-Cell circuit boards) used to convert the
eight differential CCD array outputs (four for each channel)
to single-ended signals for A/D conversion. Operation of
the Channel 1, Side 1 Gain-Cell amplifier is described.
C C D O II signal outputs from U450 pass to the
Gain-Cell board (diagram 14A), where they are applied to
the bases of U111A, U111B, U111C and U111D via R113
and R114. Transistors U111A-U111D, along with current-
source transistors Q111 and Q112, form a variable-gain
differential- current amplifier. The differential current at the
collectors of U111B and U111C is equal to the differential
current through U111A and U111D, multiplied by the ratio
of the dc current for the Q112 current source to that of
the Q 1 11 current source. Since the Q 111 current is set by
the fixed bias on the its base-emitter circuit, the gain
adjustment of the amplifier is controlled by the dc voltage
at the base of Q112, which is controlled by the System
y P
via the DAC system. The gain set is dependent on a
calibration constant determined at instrument self­
calibration.
The collectors of U111C and U111D are connected to
operational amplifier U118A, which is configured as a
differential-input, single-ended output transresistance
amplifier. The connection of R115 to the + 8 .5 V supply
causes the output of U118A to be level shifted to + 8 .5 V.
The resulting output at pin 1 of U770A (GC11) is a level-
shifted, amplified, single- ended replica of the differential
CCD array output signal, with most common-mode
interference removed.
T ra ck -a n d -H o ld A m plifiers and M ultiplexers
The Track-and-Hold Amplifiers and Multiplexers allow a
single A/D Converter to digitize all the analog samples
from all CCD arrays by time-multiplexing the output
samples to the single converter. The eight Track-and-Hold
circuits are identical; and, for brevity, only the CH 1 —
Side 1 circuitry will be described.
The GCX output from the A30 gain cell board (GC11) is
applied directly to sampling switch U560A, an
enhancement-mode M O S-FET device. The switch gate is
controlled via Q660 by the OSAM1 (Output Sample from
Channel 1) logic signal, and is closed w hen the data being
shifted out of the CCD is stable. When OSAM1 is LO, the
switch is on, and hold capacitor C774 charges to the
signal level of GC11. When OSAM1 is HI, the switch is off,
and C774 holds its voltage level. Figure 3-3 (shown previ-
ously in the “System Clocks’’ description) shows the timing
of OSAM1 and OSAM 2 during the Slow-Out and Short-
Pipe modes of CCD operation. During Fast-In mode,
OSAM1 and OSAM 2 are both held LO.
The level stored on Hold capacitor C774 is buffered by
operational amplifier U770A. The operational amplifier,
along with Q774, converts the applied input sample volt­
age to output current.
3-61