Tektronix 2440, Руководство пользователя

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Theory of Operation— 2440 Service
Registers to control the setup of the Peak Detectors, the
A/B Trigger Generator, the Trigger Logic Array, and the
Phase Clock Array. Additional decoding circuitry produces
clocking signals used to load controlling data into Attenua­
tor Register, the C H I and CH2 Preamplifiers, and the A/B
Trigger Generator.
Triggers and CCD C locks (diag ram 11)
TRIGGERS.
The Trigger circuits detect when a trigger
meeting the setup conditions occurs. Triggering signals are
selectable by the A/B Trigger Generator from a choice of
the following sources: CH 1, CH 2, EXT 1, EXT 2, and
LINE. The Trigger Logic Array makes possible the further
choices of TV Trigger (TVTG), W ORD Trigger (WDTTL), or
A and B Trigger. Upon receiving a valid trigger, the
acquisition in progress is allowed to complete. Conditions
for triggering, such as Level, Slope, Coupling, and Mode,
are determined by the A/B Trigger Generator. Other
triggering conditions such as delay by time, delay by
events, and A and B Trigger are decided by the Trigger
Logic Array which produces the output gates signaling a
trigger event. The System
nP
sets up the operating modes
for the A/B Trigger Generator and the Trigger Logic Array
via the Acquisition Control Registers (diagram 5). Control
signals to the Jitter Correction Ramps (RAM P and RAMP)
are generated by the Trigger Logic Array to start measur­
ing the time between the sample clock and the trigger
event. That time difference is used to correctly place the
samples when repetitive sampling is used.
CCD CLOCKS.
The CCD Clocks (used to move data
into and out of the CCDs), the Peak Detector Clocks, the
ramp-switching signals to the Jitter Correction Ramp
circuits, and the trigger location bits (needed to place the
trigger position with respect to the waveform data) are all
generated by the Phase Clock Array. A master clock sig­
nal of 500 MHz is generated by the Phase-Locked Loop
circuit and voltage-controlled oscillator. The master clock
frequency needed is determined by the sampling rate at a
particular SEC/DIV switch setting. Frequency dividers in
the Phase Clock Array reduce the master clock frequency
to the lower rates of the output clocks as determined by
the System /uP via the Acquisition Control Registers
(diagram 5).
Jitter Correction R am ps (diagram 12)
The Jitter Corrections Ramps work in conjunction with
the Jitter Counters to detect and measure the time
difference between a trigger event (that occurs randomly)
and the sample clock. That time difference is used to
correctly place sampled data points into the waveform
record when those samples are acquired on different
triggers (repetitive sampling). Two ramp generators are
used, so two time measurements are made. The System
uP
will determine which measurement is the one actually
used. The RAMP and RAMP signals from the Trigger cir­
cuits control the start and stop of the ramp signals while
the SLRMP1 and SLRM P2 signals control switching
between the fast-charging current source and slow-
discharging current source. Since the SLRM P signals are
related to the sample clock, the amount of charge stored
from the fast-charging current source before switching to
the slow ramp occurs is a measure of the time difference
between the trigger and the sample clock. The Jitter
Counters start counting when the SLRMP signal switches
to the slow ramp, and they are stopped when a
comparator circuit determines that the ramp level has
discharged to a fixed reference level.
T rig g er Holdoff and Jitte r C ounters (diag ram 13)
TRIGGER HOLDOFF.
The A Trigger Holdoff circuit
prevents the A/B Trigger Generator (diagram 11) from
recognizing a new trigger event for a certain amount of
delay time after an acquisition has been completed. The
delay allows all of the data handling of the acquired sam­
ples to be completed before starting a new waveform
acquisition. Minimum holdoff time is dictated by the
SEC/DIV switch setting. A front-panel HOLDOFF control
permits the user to increase the holdoff time as an aid in
improving triggering stability on certain signals.
JITTER COUNTERS. The Jitter Counters (one for
RAMP1 and one for RAMP2) start counting the 40 MHz
clock when a START signal is received from the Jitter
Counter Ramps switching circuit. That start occurs at the
beginning of the slow ramp discharge. When the level of
the slow ramp decreases to the fixed reference level, a
STOP signal generated by a comparator in the Jitter
Counter Ramps circuit halts the count. The 8-bit count
bytes held in the Jitter Counters are then read by the Sys­
tem
fiP
via address-selected bus buffers as two measures
of the time difference between the trigger point and the
sample clock. Since the timing between the two ramps is
not identical (but both times are referenced), one
measurement may have been made with better slope
characteristics than the other (over a more linear portion
of the discharge curve). The count producing the least
ambiguity is used by the System
pP
to correctly position
the waveform samples in the memory when repetitive
sampling is done.
C alibrator (diag ram 13)
The Calibrator circuitry shapes the CALCLK signal from
the Time Base Controller to produce a signal with a faster
rise and fall time and very precise amplitude. Frequency of
the Calibrator signals changes (within limits) as the
SEC/DIV switch changes. Signal amplitude is 400 mV
(starting from zero), and the effective output impedance
is 50 fi.
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