Tektronix 2440, Руководство пользователя

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Theory o f O peration— 2440 S ervice
DETAILED CIRCUIT DESCRIPTION
SYSTEM PROCESSOR
The System Processor (diagram 1) is the control center
of all operations in the scope. It consists of an 8-bit
microprocessor (^P), an 8-bit data bus, a 16-bit address
bus, a prioritizing interrupt system, hardware address
decoding, nonvolatile RAM space, and 272K bytes of
bank-switched ROM.
The System Processor circuitry also coordinates the
functions of the two other microprocessors in the 2430,
the Waveform Processor and the Front Panel Processor.
S y s te m
System ^P U640 executes instructions stored in the
System ROM in order to initiate and control the various
functions of this scope. Internally, the microprocessor has
16-bit data paths; externally it has an 8-bit data bus for
communication and a separate 16-bit address bus. No
address/data bus demultiplexing is necessary. The
n P
is
driven by an external 8-M Hz clock that is divided by four
internally for a 2-M Hz cycle rate. The number of cycles per
instruction varies from a minimum of 2 to a maximum of
20, with the average being about 4 cycles per instruction.
The mP executes, on the average, 1/2 MIP (Million Instruc­
tions Per second).
System ^P U640 generates three signals used to con­
trol the communication activities of external circuitry. Of
these signals, E and Q are for timing purposes. The rising
edge of Q signals that the address on the bus is valid;
data to the ^P is latched on the falling edge of E. The third
signal generated is the R/W signal. It is valid the same
time the address is valid, and its state (LO or HI) deter­
mines whether an addressed device is written to or read
from.
The E signal (U640 pin 34) and the Q signal (U640 pin
35) are ORed together by U840D to generate the HVMA
(Host Valid Memory Address) signal. When HVM A at
U840D pin 11 is HI, the address on the bus is valid. Once
the external circuitry receives a valid address signal, it
proceeds with the specified memory access. The signals
used to enable and time these accesses are RD (read) and
WR (write).
The RD signal is derived from U844A, which NANDs
the HVMA signal with the
n P
R/W signal. Inverting buffer
U572C provides added driving power to the R/W signal,
and inverting buffer U884B reinverts it back to its original
polarity before it is applied to NAND-gate U844A. The out­
put of U844A is the RD signal, whose falling edge indi­
cates the start of a read cycle. The rising edge of RD is
coincident with the latching of the data read into ^P U640.
The WR signal is derived from an inverted version of
the
fiP
R/W signal (via U572C) with a buffered
^ P
Q signal
(via U880D) NANDed by U844B. The output of this
NAND-gate is a signal with a falling edge that indicates the
start of a write cycle to the addressed device and a rising
edge that latches data from the
^ P
into the addressed
device. The Q signal is used here instead of HVMA (as
was used to generate RD to produce a data hold time of
more than 100 ns as needed by the oscilloscope Time
Base Controller circuitry.
D a ta B us B u ffe r
Data Bus Buffer U650 provides buffering of the data
bus lines. It is bidirectional to enable two-way communica­
tion between the System ^P and the data bus. In normal
operation, jumper J126 will connect the chip-enable pin to
ground, and the buffer is enabled to transfer data. The
direction of the transfer is controlled by the R/W signal
from the System ^P via inverting buffer U572C.
Moving test jumper J126 to its 'KERNEL'' position dis­
ables buffer U650 and forces it to its tri-state (high-
impedance output) mode. The pull-up and pull-down resis­
tors on the data bus lines, R742, R746, and R744, place
an instruction byte on the mP data bus that causes the
n P
to repeatedly increment the addresses placed on its
address bus lines through their entire range. This pro­
cedure is a troubleshooting aid that exercises a good por­
tion of the address-decoding and chip-select circuitry.
A d d re s s B u ffe rs
Address Buffers U632 and U730 provide buffering of
the System
n P
address lines to the various addressable
devices. The buffer chips are permanently enabled and
provide both current buffering and electrical isolation for
the address lines. Test point TP840 is provided as a
source of an oscilloscope trigger signal when checking the
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