Tektronix 2440, Руководство пользователя

Страница: 78 / 531

Theory of Operation— 2440 Service
After one run through the counting cycle at power-on,
any unknown counter states in divide-by-ten counter U622
are resolved, and the circuit counts in the following
manner: If the circuit does not start in the Load condition,
it will be in the Count mode (a HI on pin 9 from the output
of NAND-gate U620C) and the 20 MHz clocks cause the
counter output to increment until it reaches 1100 (binary).
At this point the output of U620C will go LO, causing the
counter to load the count 0011 (binary) from its inputs with
the next clock. Once the counter is loaded, the output of
U620C will return HI, and normal counting from a known
state commences. When the counter reaches 1100 again,
the load-count sequence will be repeated, requiring ten
20 MHz clocks to complete the cycle.
AND-gate U623C watches the three lowest bits of the
counter outputs (QA, QB, and Qc). The output of U623C
(pin 8) will be HI during the “7 ” state (0111 binary) of each
10-count cycle and will stay HI for one 20 M Hz clock cycle
(50 ns). This HI is applied to the K input and the J input
(via OR-gate U522B) of flip-flop U523B. With the K and J
inputs both HI, the flip-flop toggles when the next 20 MHz
clock arrives. Assuming the Q output of the flip-flop was
LO, toggling to a HI applies a HI to the J input via OR-gate
U522B. When the output of U623C returns LO (next
20 MHz clock), the J and K input states of the flip-flop will
keep the Q output HI with subsequent 20 M Hz clocks.
The Q output of U523B will stay HI until the next seven
(0111) state from AND-gate U623C arrives, at which time
the J and K inputs are again set HI. On the rising edge of
the next 20 MHz clock the Q output of flip-flop U523B tog­
gles LO. When the 50 ns pulse from U623C returns LO,
the J and K input states will both be LO, and further
20 M Hz clocks are prevented from changing the Q output
state of the flip-flop. The output remains LO until the next
HI state from U623C starts the divide sequence over
again. Note that transitions of the 1 M Hz signal (2XPC) at
pin 9 of U523B are delayed from the C 20M (20 M H z clock)
clock rising-edge transitions by only the propagation delay
through the flip-flop (about 7 ns).
CCD O utput-S am ple C locks
The CCD (charge-couple devices) Output-Sample
Clocks stage controls signal transfers from the Acquisition
CCD-Clock Drivers (diagram 10) to the external CCD Out­
put circuitry (diagram 14). It consists of a state machine
synchronized to the 20 MHz clock (and thus the CCD
events) and produces clocks to: (1)m ove sampled data
out of the C H I CCD array, (2) move sampled data out of
the CH2 CCD array, (3) reset both the C H I and CH2 CCD
array output-charge wells in preparation for the next
transfer, and (4) phase-lock the CCD-Data Clock stage.
Figure 3-3 illustrates the timing of these clocks and other
clocks in the System Clock Generator: it may be of use in
following the discussion of circuit operation.
When acquired samples are to be shifted out of the
C H I and CH2 CCD array, the TTL version of the Phase-
Clock 02 output (TTL2C) from Phase Clock Array U470)
will be toggling at 500 kHz. Transitions of the TTL2C clock
are resynchronized to the 20 MHz clock (C20M 2) by flip-
flop U720A to correct the phase between the TTL2C clock
and the state machine outputs. This correction closely
synchronizes charge transfers within the CCD (relative to
the 2XPC clock) with the signal transfers out of the CCD.
When the SYNC2C (synchronized phase-4 clock) is LO
(pin 5 of flip-flop U720A), the LOAD signal applied to shift
registers U730 and U830 (via AND-gate U623B and
inverter U513E) will be HI. This HI, along with the HI
SYNC2C signal from pin 6 of flip-flop U720A, causes both
shift registers to do a parallel load of the fixed logic levels
applied to their D input pins. The levels loaded set the
OS1 (sample C H I-C CD outputs), OS2 (sample CH2-CCD
outputs), and the RST (reset CCD output wells) outputs
from U730, and the SYNC (sync data clocks) output from
U830 all HI. The HI RST level applied back to U621 and
the HI output from NAND-gate U620B will be loaded into
counter U621 as 0101 binary because of the LO LOAD
output of U623B applied to the C T/ LD input pin. This
state then stays as is for the remainder of the LO state of
the SYNC2C signal.
When the SYNC2C output of flip-flop U720A returns HI,
counter U621 is enabled by the HI from AND-gate U623B
to count for three, 20 M H z clock cycles (150 ns), reaching
the count of 0111 binary. The next clock toggles the QC
output of U621 LO (count goes to 1000 binary), and the
LOAD output from AND-gate U623B is forced LO. The HI
LOAD signal output obtained from inverter U513E, along
with the LO SYNC2C from flip-flop U720A pin 6, sets up
shift registers U730 and U830 to shift right. The next
20 M Hz clock (250 ns after the 2XPC clock toggled) shifts
a LO to the OS1 output of U730 (pin 14) and toads a
binary 0100 into counter U621 (since the output of NAND-
gate U620B is now LO). The fixed HI applied to the SR
data input of U730 is shifted to the QA output.
After 0100 is loaded into counter U621, the LOAD out­
put of U623B returns HI (since pin 12 of U621 has been
set HI by the inputs loaded into the counter). This once
again produces a LO LOAD output from inverter U513E
and prevents U730 and U830 from shifting. Counter U621
counts four cycles of the 20 M Hz clock (200 ns), reaching
count 0111. The next 20 M Hz clock toggles the Qc output
of U621 LO and sets the LOAD line LO once again, ena­
bling shift registers U730 and U830. The next clock
(250 ns) shifts the previously loaded LO from the OS1 out­
put right to the OS2 output of U730 and moves a HI from
the SR data input into the OS1 output. At the same time,
counter U621 is reloaded to 0100 binary to again restart
its count.
3 -3 6