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Theory of Operation— 2440 Service
Offset Buffer. With FET Q710 turned off via U710A, the
offset line to the Channel 2 Vertical Preamplifier is open
circuited, so no trace offsetting can occur.
When the Channel 2 Vertical Display Clamp is enabled,
BCLAMPENA will be HI, turning U420D off. The LO on the
collector of U420D turns Q420 off, enabling Offset Buffer
Amplifier U710D to track the offset level output from the
active Offset Amplifier, and the offset signal line to the
Channel 2 Vertical Preamplifier is connected to the Offset
Buffer by turning on Q 710 via U710A.
Selection of either U514 or U520 is controlled by the
CH2 INV signal and is dependent on the setting of the
invert function in the associated COUPLING/INVERT
menu. Since signal offsetting in the Channel 2 Preamplifier
is done before the signal is inverted, offset voltages for
inverted- and normal-signal displays must be of opposite
polarity. Switching between these two offset amplifiers
provides the required polarity change and allows the back
porch of either display type to be clamped at the ground
reference. Depending on the polarity of the CH2 INV
(Channel 2 Invert) signal, either U410E or U410D will be
on, turning off either U410B or U410C. U410B will be off
when CH2 INV is HI and U410C will be off when it is LO.
Bias current from the Trigger Back-Porch Clamp circuit to
the offset amplifiers (U514 and U520) is not shunted away
by the "off" transistor, and the offset amplifier associated
with the off transistor will be biased on during the sync
pulse back-porch interval.
Biasing current to enable the selected Offset Amplifier
is produced during the back-porch interval when U41OA (in
the Trigger Back-Porch Clamp circuit) is turned off. Bias
current through either R411 or R410 (depending on
whether U410B or U410C is off) is supplied via R403. The
other offset amplifier will be disabled since its bias current
is being shunted through the "on” transistor. The amount
of bias current permitted by Transconductance Amplifier
U504 to the "on" amplifier provides a signal to the Chan
nel 2 Preamplifier (after buffering by U710D) that vertically
offsets the displayed signal on Channel 2.
Since the offset voltage must be maintained throughout
the entire horizontal interval, capacitor C522 (and C520 in
parallel if FASTCLAMP is not enabled) serves as a hold
capacitor
between
back-porch
samples.
At
some
VOLTS/DIV settings the Channel 2 Preamplifier is set for
higher offset gain. Transistor Q419 will be turned on for
those settings, placing C520 in parallel with C522 to slow
down the loop response. This prevents oscillation in the
Channel 2 Preamplifier at the more sensitive gain settings.
Offset Buffer Amplifier U710D applies this “stored”
offset level to the Channel 2 Preamplifier (via Q710), shift
ing the back porch of the displayed signal to near the on
screen ground reference (as set with the Vertical POSI
TION control).
Any time the Phase-Locked Loop is not locked (indicat
ing that a proper TV Trigger signal is not present), the
Channel 2 Vertical Display Clamp is turned off via R328 by
a HI TVCLAM P signal from the PLL Unlock Detector to
prevent
sending
invalid
offsets to
the
Channel
2
Preamplifier. During the unlocked state of the PLL, FET
Q 420 is biased on to pull the input to Offset Buffer
Amplifier U710D to ground, and FET Q 710 is biased off via
U710A (acting as an inverter to the TVCLAM P signal) to
open circuit the offset signal line to the Channel 2
Preamplifier.
LOW-VOLTAGE POWER SUPPLY
The low voltages required by the scope are produced
by a high-efficiency, switching power supply (diagram 22).
This type of supply directly rectifies and stores charge
from the ac line supply; then the stored charge is switched
through a special transformer at a high rate, generating
the various supply voltages.
A C P o w er Input
LINE SWITCHING AND LINE RECTIFIER.
Ac line volt
ages of either 1 1 5 V or 230 V may provide the primary
power for the instrument, depending on the setting of the
LINE VOLTAGE SELECTOR switch S1000 (located on the
instrument rear panel). POWER Switch S I 350 applies the
selected line voltage to the power supply rectifier (CR510).
With the selector switch in the 115 V position, the
rectifier and storage capacitors C l 05 and C305 operate as
a full-wave voltage doubler. When operating in this
configuration, each capacitor is charged on opposite half
cycles of the ac input, and the voltages across the two
capacitors in series approximates the peak-to-peak values
of the source voltage. For 230 V operation, switch S I 000
connects the rectifier as a conventional bridge rectifier.
Both capacitors charge on both input half cycles, and the
voltage across C l 05 and C305 in series approximates the
peak value of the rectified source voltage. For either
configuration (with proper line voltage), the dc voltage sup
plied to the power supply inverter is the same.
SURGE PROTECTION.
Thermistors RT717 and RT805
limit the surge current when the power supply is first
turned on. As current warms the thermistors, their resist
ances decrease and have little effect on circuit operation.
3 -9 2
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