Tektronix 2440, Руководство пользователя

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Theory of Operation—2440 Service
frequency switching, and much more efficient power
transfer is possible. Regulation of the power to the switch­
ing transformer is controlled by a pulse-width modulator
(PW M ) using feedback from one of the rectifier
transformer outputs. The PWM controls the on-time of the
switching transistors that deliver energy to the transformer
primary winding. If the feedback voltage is too low, more
energy is supplied by turning on the switching transistors
longer. Automatic overvoltage and overcurrent sensing cir­
cuits shut down the switching if either type of overload
occurs. The ac input has an interference filter, primary line
fusing, and a thermal cutout that shuts down the power
supply in the event of overheating.
Low V o ltage R egulators (diagram 23)
The Low Voltage Regulators remove ac noise and rip­
ple from the rectified output voltages from the power
transform er. Each regulator automatically current limits the
output and prevents the current from exceeding the nor­
mal power limits. This limiting prevents further possible
damage to the power supply or other scope circuitry. Each
of the power supply regulators controls its output voltage
level by comparing the output to a known voltage refer­
ence level. To maintain stable and well-regulated output
voltages, highly stable reference voltages are developed
for making the comparisons.
DETAILED BLOCK DIAGRAM DESCRIPTION
INTRODUCTION
This description of the Detailed Block Diagram (found in
the “Diagrams” section of this manual) provides an over­
view of the operation of many of the circuits and their
functions. The emphasis is on the acquisition system, and
a “signal flow ” approach is used as much as possible. No
attem pt is made in this discussion to specifically cover all
the circuitry shown on the block diagram, though most is
covered in general as it relates to those areas described in
detail. The components discussed for each schematic
diagram are generally outlined in functional blocks on their
corresponding schematic diagram. These “function blocks’
also appear on the “Detailed Block Diagram ” within out­
lined areas that correspond to the schematic diagrams.
Refer to both the Detailed Block Diagram and the
Schematic Diagrams as needed while reading the
following description.
INPUT SIGNAL CONDITIONING
AND ANALOG SAMPLING
Signals applied to the CH 1 and CH 2 input connectors
are coupled to their respective attenuators. The CH 1 and
CH 2 attenuators (diagram 9) are settable for IX , 10X, and
100X attenuation, with input-coupling mode choices of AC,
DC, and GND. Input termination resistance of either 1 MO
or 50 0 is selectable with the DC input coupling choice.
The attenuation factor, input coupling mode, and input ter­
mination settings for each input are controlled by the Sys­
tem
iiP
(diagram 1) through the Attenuator Control Regis­
ter (diagram 9), based on the Front Panel control settings
chosen by the user.
The attenuated CH 1 and CH 2 signals are buffered by
their respective Preamps (diagram 9) before they are
passed on to the Peak Detectors. Preamplifier gain is con­
trolled by the System
pP
using a serial control-data line via
the Miscellaneous Register (diagram 1) and the DAC M UX
(digital-to-analog converter multiplexer) Select circuit.
Serial data is clocked into the internal register of the
Preamps via the Control Register Clock Decoder
(diagram 5). As with the attenuator settings, the gain­
setting data output by the System
pP
depends on the
user-selected Front Panel control settings. The range of
attenuation settings coupled with the gain-control settings
o f the Preamps allows the complete range of available
V O LTS/D IV switch settings (from 2 mV to 5 V) to be
obtained.
In addition to signal gain and input signal buffering, the
Preamps convert the single-ended input signal to a
double-ended differential output signal that improves the
common-mode rejection ratio. Input ports used to control
the DC Balance, the Variable V O LTS/D IV gain, and the
Vertical Position are provided in the Preamp stages. Ana­
log control voltages to these inputs are developed by the
System DAC and routed to the Preamps via the DAC
M U X /0 Sample-and-Hold circuit (diagram 5). Trigger pickoff
circuits in each Preamp provide a sample of the vertical
signal that may be selected by the Trigger circuitry as the
trigger signal source.
The differential output signals from the Preamps are
applied to their corresponding Peak Detector. Input
amplifiers within the CH 1 and CH 2 Peak Detectors
(diagram
10
) buffer the applied signals and provide a con­
stant input resistance of about 75 0 to those signals. The
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