Offset
Name
Description
0x00
sckdiv
Serial clock divisor
0x04
sckmode
Serial clock mode
0x08
Reserved
0x0C
Reserved
0x10
csid
Chip select ID
0x14
csdef
Chip select default
0x18
csmode
Chip select mode
0x1C
Reserved
0x20
Reserved
0x24
Reserved
0x28
delay0
Delay control 0
0x2C
delay1
Delay control 1
0x30
Reserved
0x34
Reserved
0x38
Reserved
0x3C
Reserved
0x40
fmt
Frame format
0x44
Reserved
0x48
txdata
Tx FIFO Data
0x4C
rxdata
Rx FIFO data
0x50
txmark
Tx FIFO watermark
0x54
rxmark
Rx FIFO watermark
0x58
Reserved
0x5C
Reserved
0x60
fctrl
SPI flash interface control*
0x64
ffmt
SPI flash instruction format*
0x68
Reserved
0x6C
Reserved
0x70
ie
SPI interrupt enable
0x74
ip
SPI interrupt pending
Serial Clock Divisor Register (
The
sckdiv
is a
div_width
-bit register that specifies the divisor used for generating the serial
clock (SCK). The relationship between the input clock and SCK is given by the following for-
mula:
Table 65:
Register offsets within the SPI memory map. Registers marked * are present only on
controllers with the direct-map flash interface.
Copyright © 2019, SiFive Inc. All rights reserved.
86
Содержание FE310-G002
Страница 1: ...SiFive FE310 G002 Manual v19p05 SiFive Inc ...
Страница 11: ...Figure 1 FE310 G002 top level block diagram Copyright 2019 SiFive Inc All rights reserved 9 ...
Страница 15: ...Chapter 2 List of Abbreviations and Terms 13 ...
Страница 23: ...Chapter 4 Memory Map The memory map of the FE310 G002 is shown in Table 4 21 ...