Receive Control Register (
rxctrl
)
Register Offset
0xC
Bits
Field Name
Attr.
Rst.
Description
0
rxen
RW
0x0
Receive enable
[15:1]
Reserved
[18:16]
rxcnt
RW
0x0
Receive watermark level
[31:19]
Reserved
The
ip
register is a read-only register indicating the pending interrupt conditions, and the read-
write
ie
register controls which UART interrupts are enabled.
ie
is reset to
0
.
The
txwm
condition becomes raised when the number of entries in the transmit FIFO is strictly
less than the count specified by the
txcnt
field of the
txctrl
register. The pending bit is
cleared when sufficient entries have been enqueued to exceed the watermark.
The
rxwm
condition becomes raised when the number of entries in the receive FIFO is strictly
greater than the count specified by the
rxcnt
field of the
rxctrl
register. The pending bit is
cleared when sufficient entries have been dequeued to fall below the watermark.
UART Interrupt Enable Register (
ie
)
Register Offset
0x10
Bits
Field Name
Attr.
Rst.
Description
0
txwm
RW
0x0
Transmit watermark interrupt enable
1
rxwm
RW
0x0
Receive watermark interrupt enable
[31:2]
Reserved
UART Interrupt Pending Register (
ip
)
Register Offset
0x14
Bits
Field Name
Attr.
Rst.
Description
0
txwm
RO
X
Transmit watermark interrupt pending
1
rxwm
RO
X
Receive watermark interrupt pending
[31:2]
Reserved
The read-write,
div_width
-bit
div
register specifies the divisor used by baud rate generation
for both Tx and Rx channels. The relationship between the input clock and baud rate is given by
the following formula:
Table 59:
Receive Control Register
Table 60:
UART Interrupt Enable Register
Table 61:
UART Interrupt Pending Register
Copyright © 2019, SiFive Inc. All rights reserved.
82
Содержание FE310-G002
Страница 1: ...SiFive FE310 G002 Manual v19p05 SiFive Inc ...
Страница 11: ...Figure 1 FE310 G002 top level block diagram Copyright 2019 SiFive Inc All rights reserved 9 ...
Страница 15: ...Chapter 2 List of Abbreviations and Terms 13 ...
Страница 23: ...Chapter 4 Memory Map The memory map of the FE310 G002 is shown in Table 4 21 ...