mtime
is a 64-bit read-write register that contains the number of cycles counted from the
rtcclk
input described in Chapter 13. A timer interrupt is pending whenever
mtime
is greater than or
equal to the value in the
mtimecmp
register. The timer interrupt is reflected in the
mtip
bit of the
mip
register described in Chapter 8.
On reset,
mtime
is cleared to zero. The
mtimecmp
registers are not reset.
Copyright © 2019, SiFive Inc. All rights reserved.
43
Содержание FE310-G002
Страница 1: ...SiFive FE310 G002 Manual v19p05 SiFive Inc ...
Страница 11: ...Figure 1 FE310 G002 top level block diagram Copyright 2019 SiFive Inc All rights reserved 9 ...
Страница 15: ...Chapter 2 List of Abbreviations and Terms 13 ...
Страница 23: ...Chapter 4 Memory Map The memory map of the FE310 G002 is shown in Table 4 21 ...