Debug-mode breakpoint traps jump to the debug trap vector without altering machine-mode reg-
isters.
Machine-mode breakpoint traps jump to the exception vector with "Breakpoint" set in the
mcause
register and with
badaddr
holding the instruction or data address that caused the trap.
Sharing Breakpoints Between Debug and Machine Mode
When debug mode uses a breakpoint register, it is no longer visible to machine mode (that is,
the
tdrtype
will be 0). Typically, a debugger will leave the breakpoints alone until it needs them,
either because a user explicitly requested one or because the user is debugging code in ROM.
This section describes the debug module’s memory map when accessed via the regular system
interconnect. The debug module is only accessible to debug code running in debug mode on a
hart (or via a debug transport module).
Debug RAM and Program Buffer (
The FE310-G002 has 16 32-bit words of program buffer for the debugger to direct a hart to exe-
cute arbitrary RISC-V code. Its location in memory can be determined by executing
aiupc
instructions and storing the result into the program buffer.
The FE310-G002 has one 32-bit words of debug data RAM. Its location can be determined by
reading the
DMHARTINFO
register as described in the RISC-V Debug Specification. This RAM
space is used to pass data for the Access Register abstract command described in the RISC-V
Debug Specification. The FE310-G002 supports only general-purpose register access when
harts are halted. All other commands must be implemented by executing from the debug pro-
gram buffer.
In the FE310-G002, both the program buffer and debug data RAM are general-purpose RAM
and are mapped contiguously in the Core Complex memory space. Therefore, additional data
can be passed in the program buffer, and additional instructions can be stored in the debug data
RAM.
Debuggers must not execute program buffer programs that access any debug module memory
except defined program buffer and debug data addresses.
The FE310-G002 does not implement the
DMSTATUS.anyhavereset
or
DMSTATUS.allhavereset
bits.
This ROM region holds the debug routines on SiFive systems. The actual total size may vary
between implementations.
Copyright © 2019, SiFive Inc. All rights reserved.
109
Содержание FE310-G002
Страница 1: ...SiFive FE310 G002 Manual v19p05 SiFive Inc ...
Страница 11: ...Figure 1 FE310 G002 top level block diagram Copyright 2019 SiFive Inc All rights reserved 9 ...
Страница 15: ...Chapter 2 List of Abbreviations and Terms 13 ...
Страница 23: ...Chapter 4 Memory Map The memory map of the FE310 G002 is shown in Table 4 21 ...