SiFive FE310-G002, Руководство пользователя

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Chapter 3
E31 RISC-V Core
This chapter describes the 32-bit E31 RISC‑V processor core used in the FE310-G002. The
E31 processor core comprises an instruction memory system, an instruction fetch unit, an exe-
cution pipeline, a data memory system, and support for global, software, and timer interrupts.
The E31 feature set is summarized in Table 2.
Feature Description
ISA RV32IMAC.
Instruction Cache 16 KiB 2-way instruction cache.
Instruction Tightly Integrated Memory The E31 has support for an ITIM with a maxi-
mum size of 8 KiB.
Data Tightly Integrated Memory 16 KiB DTIM.
Modes The E31 supports the following modes:
Machine Mode, User Mode.
Table 2: E31 Feature Set
3.1 Instruction Memory System
The instruction memory system consists of a dedicated 16 KiB 2-way set-associative instruction
cache. The access latency of all blocks in the instruction memory system is one clock cycle. The
instruction cache is not kept coherent with the rest of the platform memory system. Writes to
instruction memory must be synchronized with the instruction fetch stream by executing a
FENCE.I instruction.
The instruction cache has a line size of 32 bytes, and a cache line fill triggers a burst access.
The core caches instructions from executable addresses, with the exception of the Instruction
Tightly Integrated Memory (ITIM), which is further described in Section 3.1.1. See the
FE310-G002 Memory Map in Chapter 4 for a description of executable address regions that are
denoted by the attribute X.
Trying to execute an instruction from a non-executable address results in a synchronous trap.
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