Instance
Flash Controller
Address
cs_width
div_width
QSPI 0
Y
0x10014000
1
12
SPI 1
N
0x10024000
4
12
SPI 2
N
0x10034000
1
12
Table 64:
SPI Instances
The memory map for the SPI control registers is shown in Table 65. The SPI memory map has
been designed to require only naturally-aligned 32-bit memory accesses.
Copyright © 2019, SiFive Inc. All rights reserved.
85
Содержание FE310-G002
Страница 1: ...SiFive FE310 G002 Manual v19p05 SiFive Inc ...
Страница 11: ...Figure 1 FE310 G002 top level block diagram Copyright 2019 SiFive Inc All rights reserved 9 ...
Страница 15: ...Chapter 2 List of Abbreviations and Terms 13 ...
Страница 23: ...Chapter 4 Memory Map The memory map of the FE310 G002 is shown in Table 4 21 ...