Trace and Debug Select Register
CSR
tselect
Bits
Field Name
Attr.
Description
[31:0]
index
WARL
Selection index of trace and debug registers
Table 100:
tselect
CSR
The
index
field is a
WARL
field that does not hold indices of unimplemented TDRs. Even if
index
can hold a TDR index, it does not guarantee the TDR exists. The
type
field of
tdata1
must be inspected to determine whether the TDR exists.
Trace and Debug Data Registers (
The
tdata1-3
registers are XLEN-bit read/write registers selected from a larger underlying
bank of TDR registers by the
tselect
register.
Trace and Debug Data Register 1
CSR
tdata1
Bits
Field Name
Attr.
Description
[27:0]
TDR-Specific Data
[31:28]
type
RO
Type of the trace & debug register selected
by
tselect
Table 101:
tdata1
CSR
Trace and Debug Data Registers 2 and 3
CSR
tdata2/3
Bits
Field Name
Attr.
Description
[31:0]
TDR-Specific Data
Table 102:
tdata2/3
CSRs
The high nibble of
tdata1
contains a 4-bit
type
code that is used to identify the type of TDR
selected by
tselect
. The currently defined
types
are shown below:
Type
Description
0
No such TDR register
1
Reserved
2
Address/Data Match Trigger
≥ 3
Reserved
Table 103:
tdata
Types
The
dmode
bit selects between debug mode (
dmode
=1) and machine mode (
dmode
=1) views of
the registers, where only debug mode code can access the debug mode view of the TDRs. Any
Copyright © 2019, SiFive Inc. All rights reserved.
105
Содержание FE310-G002
Страница 1: ...SiFive FE310 G002 Manual v19p05 SiFive Inc ...
Страница 11: ...Figure 1 FE310 G002 top level block diagram Copyright 2019 SiFive Inc All rights reserved 9 ...
Страница 15: ...Chapter 2 List of Abbreviations and Terms 13 ...
Страница 23: ...Chapter 4 Memory Map The memory map of the FE310 G002 is shown in Table 4 21 ...