Copyright © Siemens AG 2010. All rights reserved.
Page
6
ERTEC 400 Manual
Technical data subject to change
Version 1.2.2
4.4.2
F-Timer Register Description ......................................................................................................... 42
4.5
Watchdog Timers ................................................................................................................................... 43
4.5.1
Watchdog Timer 0.......................................................................................................................... 43
4.5.2
Watchdog Timer 1.......................................................................................................................... 43
4.5.3
Watchdog Interrupt ........................................................................................................................ 43
4.5.4
WDOUT0_N................................................................................................................................... 43
4.5.5
WDOUT1_N................................................................................................................................... 43
4.5.6
Watchdog Registers....................................................................................................................... 44
4.5.7
Address Assignment of Watchdog Registers................................................................................. 44
4.5.8
Watchdog Register Description ..................................................................................................... 44
4.6
UART1/ UART2...................................................................................................................................... 46
4.6.1
Address Assignment of UART 1/2 Registers ................................................................................. 48
4.6.2
UART 1/2 Register Description ...................................................................................................... 48
4.7
Synchronous Interface SPI..................................................................................................................... 52
4.7.1
Address Assignment of SPI Register ............................................................................................. 53
4.7.2
SPI Register Description................................................................................................................ 54
4.8
System Control Register ........................................................................................................................ 56
4.8.1
Address Assignment of System Control Registers ........................................................................ 56
4.8.2
System Control Register Description ............................................................................................. 57
5
General Hardware Functions ................................................................................................63
5.1
Clock Generation and Clock Supply....................................................................................................... 63
5.1.1
Clock Supply in ERTEC 400 .......................................................................................................... 63
5.1.2
PCI Clock Supply ........................................................................................................................... 64
5.1.3
LBU Clock Supply .......................................................................................................................... 64
5.1.4
JTAG Clock Supply........................................................................................................................ 64
5.1.5
Ethernet Interface Clock Supply .................................................................................................... 64
5.2
Reset Logic of the ERTEC 400 .............................................................................................................. 65
5.2.1
Hardware Reset............................................................................................................................. 65
5.2.2
Watchdog Reset ............................................................................................................................ 66
5.2.3
Software reset................................................................................................................................ 66
5.2.4
PCI bridge reset............................................................................................................................. 66
5.2.5
Actions when HW Reset is Active .................................................................................................. 66
5.3
Address Space and Timeout Monitoring ................................................................................................ 67
5.3.1
AHB Bus Monitoring....................................................................................................................... 67
5.3.2
APB Bus Monitoring....................................................................................................................... 67
5.3.3
EMIF Monitoring............................................................................................................................. 67
5.3.4
PCI Slave Monitoring ..................................................................................................................... 67
6
External Memory Interface (EMIF) ........................................................................................69
6.1
Address Assignment of EMIF Registers................................................................................................. 70
6.2
EMIF Register Description ..................................................................................................................... 70
7
Local Bus Unit (LBU). ............................................................................................................74
7.1
Page Range Setting ............................................................................................................................... 75
7.2
Page Offset Setting ................................................................................................................................ 75
7.3
Page Control Setting .............................................................................................................................. 76
7.3.1
LBU Read from ERTEC 400 with separate Read/Write line (LBU_RDY_N active low) ................. 77
7.3.2
LBU Write to ERTEC 400 with separate Read/Write line (LBU_RDY_N active low)...................... 78
7.3.3
LBU Read from ERTEC 400 with common Read/Write line (LBU_RDY_N active low).................. 79
7.3.4
LBU Write to ERTEC 400 with common Read/Write line (LBU_RDY_N active low) ...................... 80
7.4
Address Assignment of LBU Registers .................................................................................................. 81
7.5
LBU Register Description ....................................................................................................................... 82
8
PCI Interface ...........................................................................................................................83
8.1
PCI Functionality .................................................................................................................................... 83
8.1.1
General Functions of the PCI Interface:......................................................................................... 83
8.1.2
PCI Master Interface: ..................................................................................................................... 83
8.1.3
PCI Target Interface:...................................................................................................................... 84
8.1.4
Combination of PCI-master/target operation:................................................................................. 84
8.1.5
PCI Interrupt Handling: .................................................................................................................. 85
8.1.6
PCI Power Management:............................................................................................................... 87
8.1.7
Accesses to the AHB Bus: ............................................................................................................. 87
8.2
ERTEC 400 Applications with PCI:......................................................................................................... 88
8.2.1
ERTEC 400 in a PC System .......................................................................................................... 88
8.2.2
ERTEC 400 as a Station on the Local PCI Bus ............................................................................. 89
8.3
Address Assignment of PCI Register ..................................................................................................... 90