58
Figure 6-67 Simple PLC Operation
In Figure 6-67, a1~a7, d1~d7 are the Acc and Dec time of the respective
stage; f1~f7 and T1~T7 will be defined in later parameters.
The PLC stage and PLC cycle are indicated by the 500mS signals from
output terminals Y1 and Y2 of open collector output or relay output.
See F6.00~F6.02.
Figure 6-68 Stop after a Single PLC Cycle
FD.00 Simple PLC mode
Range
：
0000
～
1123
【
0000
】
f
1
f
2
f
3
f
4
f
5
f
6
f
7
T
1
T
2
T
3
T
4
T
5
T
6
T
7
a
1
a
2
a
3
d
3
a
4
d
5
a
5
a
6
d
7
d
7
Simple
PLC
500m
Signal of completing one PLC stage
Signal of completing one PLC cycle
