CHAPTER 20 STANDBY FUNCTION
Page 734 of 920
Remark
Operation stopped: Operation is automatically stopped before switching to the HALT mode.
Operation disabled: Operation is stopped before switching to the HALT mode.
f
IH
: High-speed on-chip oscillator clock
f
IL
: Low-speed on-chip oscillator clock
f
X
: X1 clock
f
EX
: External main system clock
f
XT
: XT1 clock
f
EXS
: External subsystem clock
Table 20 - 1 Operating Statuses in HALT Mode (1/2)
HALT Mode Setting
Item
When HALT Instruction is Executed While CPU is Operating on Main System Clock
When CPU is Operating on High-
speed On-chip Oscillator Clock (f
IH
)
When CPU is Operating
on X1 Clock (f
X
)
When CPU is Operating on
External Main System Clock (f
EX
)
System clock
Clock supply to the CPU is stopped
Main system
clock
f
IH
Operation continues (cannot
be stopped)
Operation disabled
f
X
Operation disabled
Operation continues
(cannot be stopped)
Cannot operate
f
EX
Cannot operate
Operation continues
(cannot be stopped)
Subsystem
clock
f
XT
Status before HALT mode was set is retained
f
EXS
Low-speed on-
chip oscillator
clock
f
IL
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and
WUTMMCK0 bit of subsystem clock supply mode control register (OSMC)
• WUTMMCK0 = 1: Oscillates
• WUTMMCK0 = 0 and WDTON = 0: Stops
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops
CPU
Operation stopped
Code flash memory
Data flash memory
RAM
Operation stopped (Operable while in the DTC is executed)
Port (latch)
Status before HALT mode was set is retained
Timer array unit
Operable
Real-time clock (RTC)
12-bit Interval timer
Watchdog timer
See
.
Timer RJ
Operable
Clock output/buzzer output
A/D converter
Serial array unit (SAU)
Serial interface (IICA)
Data transfer controller (DTC)
Event link controller (ELC)
Operable function blocks can be linked
Power-on-reset function
Operable
Voltage detection function
External interrupt
CRC operation
function
High-speed CRC
General-purpose CRC
In the calculation of the RAM area, operable when DTC is executed only
Illegal-memory access detection function
Operable when DTC is executed only
RAM parity error detection function
RAM guard function
SFR guard function
Содержание RL78/G1H
Страница 941: ...R01UH0575EJ0120 RL78 G1H...