Renesas RL78/G1H, Руководство пользователя

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RL78/G1H CHAPTER 20 STANDBY FUNCTION
R01UH0575EJ0120 Rev. 1.20 Page 735 of 920
Dec 22, 2016
Remark Operation stopped: Operation is automatically stopped before switching to the HALT mode.
Operation disabled: Operation is stopped before switching to the HALT mode.
f
IH
: High-speed on-chip oscillator clock f
IL
: Low-speed on-chip oscillator clock
f
X
: X1 clock f
EX
: External main system clock
f
XT
: XT1 clock f
EXS
: External subsystem clock
Table 20 - 2 Operating Statuses in HALT Mode (2/2)
HALT Mode Setting
Item
When HALT Instruction is Executed While CPU is Operating on Subsystem Clock
When CPU is Operating on XT1 Clock
(f
XT
)
When CPU is Operating on External
Subsystem Clock (f
EXS
)
System clock Clock supply to the CPU is stopped
Main system
clock f
IH
Operation disabled
f
X
f
EX
Subsystem
clock f
XT
Operation continues (cannot be stopped) Cannot operate
f
EXS
Cannot operate Operation continues (cannot be stopped)
Low-speed
on-chip
oscillator
clock f
IL
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0
bit of subsystem clock supply mode control register (OSMC)
• WUTMMCK0 = 1: Oscillates
• WUTMMCK0 = 0 and WDTON = 0: Stops
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops
CPU Operation stopped
Code flash memory
Data flash memory
RAM
Operation stopped (Operable while in the DTC is executed)
Port (latch) Status before HALT mode was set is retained
Timer array unit Operates when the RTCLPC bit is 0 (operation is disabled when the RTCLPC bit is not 0).
Real-time clock (RTC) Operable
12-bit Interval timer
Watchdog timer
See CHAPTER 12 WATCHDOG TIMER .
Timer RJ Operates when the RTCLPC bit is 0 (operation is disabled when the RTCLPC bit is not 0).
Clock output/buzzer output
A/D converter
Operation disabled
Serial array unit (SAU) Operates when the RTCLPC bit is 0 (operation is disabled when the RTCLPC bit is not 0).
Serial interface (IICA) Operation disabled
Data transfer controller (DTC) Operates when the RTCLPC bit is 0 (operation is disabled when the RTCLPC bit is not 0).
Event link controller (ELC) Operable function blocks can be linked
Power-on-reset function Operable
Voltage detection function
External interrupt
CRC operation
function
High-speed CRC Operation disabled
General-purpose CRC In the calculation of the RAM area, operable when DTC is executed only
Illegal-memory access detection function Operable when DTC is executed only
RAM parity error detection function
RAM guard function
SFR guard function