Renesas RL78/G1H, Руководство пользователя

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RL78/G1H CHAPTER 6 CLOCK GENERATOR
R01UH0575EJ0120 Rev. 1.20 Page 109 of 920
Dec 22, 2016
Figure 6 - 6 Format of Oscillation stabilization time select register (OSTS)
Caution 1. Change the setting of the OSTS register before setting the MSTOP bit of the clock operation status
control register (CSC) to 0.
Caution 2. The oscillation stabilization time counter counts up to the oscillation stabilization time set by the
OSTS register.
In the following cases, set the oscillation stabilization time of the OSTS register to the value greater
than the count value which is to be checked by the OSTC register after the oscillation starts.
• When the X1 clock starts oscillation while the high-speed on-chip oscillator clock or subsystem
clock is being used as the CPU clock.
• When the STOP mode is entered and then released while the high-speed on-chip oscillator clock is
being used as the CPU clock with the X1 clock oscillating. (Note, therefore, that only the status up
to the oscillation stabilization time set by the OSTS register is set to the OSTC register after the
STOP mode is released.)
Caution 3. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts
(“a” below).
Remark f
X
: X1 clock oscillation frequency
Address: FFFA3H After reset: 07H R/W
Symbol 7 6 5 4 3 2 1 0
OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0
OSTS2 OSTS1 OSTS0
Oscillation stabilization time selection
f
X
= 10 MHz f
X
= 20 MHz
0 0 0
2
8
/f
X
25.6 μ s 12.8 μ s
0 0 1
2
9
/f
X
51.2 μ s 25.6 μ s
0 1 0 2 10 /f
X
102 μ s 51.2 μ s
0 1 1 2 11 /f
X
204
μ
s 102
μ
s
1 0 0 2 13 /f
X
819
μ
s 409
μ
s
1 0 1
2
15
/f
X
3.27 ms 1.63 ms
1 1 0
2
17
/f
X
13.1 ms 6.55 ms
1 1 1
2
18
/f
X
26.2 ms 13.1 ms
STOP mode release
X1 pin voltage
waveform
a