Renesas RL78/G1H, Руководство пользователя

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RL78/G1H CHAPTER 9 REAL-TIME CLOCK
R01UH0575EJ0120 Rev. 1.20 Page 243 of 920
Dec 22, 2016
Figure 9 - 6 Format of Real-time clock control register 1 (RTCC1) (2/2)
Caution 1. If writing is performed to the RTCC1 register with a 1-bit manipulation instruction, the RIFG flag and
WAFG flag may be cleared. Therefore, to perform writing to the RTCC1 register, be sure to use an 8-
bit manipulation instruction. To prevent the RIFG flag and WAFG flag from being cleared during
writing, disable writing by setting 1 to the corresponding bit. If the RIFG flag and WAFG flag are not
used and the value may be changed, the RTCC1 register may be written by using a 1-bit manipulation
instruction.
Caution 2. RWAIT bit functions while RTCE bit is "1". When RTCE is set to 1 and RWAIT is set to 1 within one
clock cycle of f
RTC
, setting RTCE bit to "1" takes one clock cycle of f
RTC
. Therefore, it takes up to two
clock cycles of f
RTC
until the counter value can be read or written (RWST = 1).
Caution 3. When RTCE is set to 1 and RWAIT is set to 1 within one clock cycle of f
RTC
after returned from
standby (HALT/STOP/SNOOZE) mode, it takes up to two clock cycles of f
RTC
until the counter value
can be read or written (RWST = 1).
Remark 1. Fixed-cycle interrupts and alarm match interrupts use the same interrupt source (INTRTC). When using
these two types of interrupts at the same time, which interrupt occurred can be judged by checking the fixed-
cycle interrupt status flag (RIFG) and the alarm detection status flag (WAFG) upon INTRTC occurrence.
Remark 2. The internal counter (16 bits) is cleared when the second count register (SEC) is written.
RIFG Constant-period interrupt status flag
0 Fixed-cycle interrupt is not generated.
1 Fixed-cycle interrupt is generated.
This flag indicates the status of generation of the fixed-cycle interrupt. When the fixed-cycle interrupt is generated, it is
set to “1”.
This flag is cleared when “0” is written to it. Writing “1” to it is invalid.
RWST Wait status flag of real-time clock
0 Counter is operating.
1 Mode to read or write counter value
This status flag indicates whether the setting of the RWAIT bit is valid.
Before reading or writing the counter value, confirm that the value of this flag is 1.
RWAIT Wait control of real-time clock
0 Sets counter operation.
1 Stops SEC to YEAR counters. Mode to read or write counter value
This bit controls the operation of the counter.
Be sure to write “1” to it to read or write the counter value.
As the internal counter (16-bit) is continuing to run, complete reading or writing within one second and turn back to 0.
When RWAIT = 1, it takes up to one cycle of f
RTC
until the counter value can be read or written (RWST = 1).
When the internal counter (16-bit) overflowed while RWAIT = 1, it keeps the event of overflow until RWAIT = 0, then
counts up.
However, when it wrote a value to second count register, it will not keep the overflow event.