Ossila FACT1, Руководство пользователя

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Auto Zero sets the Auto Zero for the DRAIN SMU, refer to the IV GATE section above for more
information.
Drain Voltage (Linear Region) selects the value V
DS
that the DRAIN source applies to the target, with
V
DS
drain voltage for which the target transistor is operating in Linear Mode, as it appears in the I-V
curves when I
DS
= α V
DS
, with α proportionality constant. Usually, Drain Voltage (Linear Region) for
organic transistors is approximately 5% to 10% of the drain voltage at which the transistor is
operating in saturation mode.
Drain Voltage (Saturation Mode) is the drain voltage at which the transistor operates in saturation
mode, i.e. I
DS
( V
DS
) = I
sat
, with I
sat
constant drain saturation current reads from the I-V Output
Characteristic curves.
Delay is the PXI DRAIN settling time. For Transfer Characteristic OFF

ON measurement indicative
DRAIN and GATE Delay time are 10 to 200 ms and 10 to 100 ms, respectively. The actual delay time
depends on dielectric capacitance, organic semiconductor, device architecture and measurement
settings.
Current Limit specifies the maximum drain current ( I
DS
) that the DRAIN source is allowed to generate
across the target (OFET, for example) as the User’s selected gate voltages are applied to the target
itself, i.e. Current Limit refers to
I
DS
( V
GS
) for any V
DS
applied.
Data analysis: Transistor parameters
Channel length table is used to enter the OFET/TFT channel length (in μm) for the DUTs that have
been previously selected on the Measurement Settings and Device Parameters UI. The input table
field needs to be enabled by selecting one of the options on the ring selector below the table itself.
Channel length ring selector allows the user to select the appropriate substrate (channel length)
layout. The available options are:
User Selection. The User directly input the channel length using the Channel Length table.
This option allows to individually enter the DUTs channel length, one at the time.