CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
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Priorities 0 to 7 (0 is the highest) can be programmed for each maskable interrupt request for multiple interrupt
processing control. To set a priority level, write values to the xxPRn0 to xxPRn2 bits of the interrupt request control
register (xxICn) corresponding to each maskable interrupt request. At reset, the interrupt request is masked by the
xxMKn bit, and the priority level is set to 7 by the xxPRn0 to xxPRn2 bits.
Priorities of maskable interrupts
(High) Level 0 > Level 1 > Level 2 > Level 3 > Level 4 > Level 5 > Level 6 > Level 7 (Low)
Interrupt servicing that has been suspended as a result of multiple interrupt servicing is resumed after the interrupt
servicing of the higher priority has been completed and the RETI instruction has been executed.
A pending interrupt request is acknowledged after the current interrupt servicing has been completed and the
RETI instruction has been executed.
Caution In the non-maskable interrupt servicing routine (time until the RETI instruction is executed),
maskable interrupts are not acknowledged but are suspended.
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