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CHAPTER 4 BUS CONTROL FUNCTION
User’s Manual U13850EJ4V0UM
112
4.6 Idle State Insertion Function
To facilitate interfacing with low-speed memory devices and meeting the data output float delay time on memory
read accesses every two blocks, one idle state (TI) can be inserted into the current bus cycle after the T3 state. The
bus cycle following continuous bus cycles starts after one idle state.
Specifying insertion of the idle state is programmable by using the bus cycle control register (BCC).
Immediately after the system has been reset, idle state insertion is automatically programmed for all memory
blocks.
(1) Bus cycle control register (BCC)
This register can be read/written in 16-bit units.
Figure 4-9. Bus Cycle Control Register (BCC)
After reset: AAAAH
R/W
Address: FFFFF062H
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BCC
Idle state insert specification
0
Not inserted
1
Inserted
n
Blocks into which idle state is inserted
0
Blocks 0/1
1
Blocks 2/3
2
Blocks 4/5
3
Blocks 6/7
4
Blocks 8/9
5
Blocks 10/11
6
Blocks 12/13
7
Blocks 14/15
Block 0 is reserved for the internal ROM area; therefore, no idle state can be specified.
The internal RAM area and on-chip peripheral I/O area of block 15 are not subject to insertion of the idle state.
Be sure to set bits 0, 2, 4, 6, 8, 10, 12, and 14 to 0. If these bits are set to 1, the operation is not guaranteed.
0
BC01
0
BC11
0
BC21
0
BC31
0
BC41
0
BC51
0
BC61
0
BC71
BCn1
Содержание MPD703030A
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