Nations Technologies Inc.
Tel
:
+86-755-86309900
:
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
473
/
631
Figure 22-16 USART data clock timing example (WL=1)
Figure 22-17 RX data sampling / holding time
Note: the function of CK is different in Smartcard mode, please refer to the Smartcard mode section for details.
Single-wire half-duplex mode
USART supports single-wire half-duplex communication, allowing data to be transmitted in both directions, but only
Clock
(
CLKPOL=0
,
CLKPHA=0
)
Clock
(
CLKPOL=0
,
CLKPHA=1
)
Clock
(
CLKPOL=1
,
CLKPHA=0
)
Clock
(
CLKPOL=1
,
CLKPHA=1
)
Data on TX
(from master)
Data on RX
(from slave)
Start LSB
MSB Stop
MSB
LSB
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
valid DATA bit
SCLK(capture strobe on SCLK
rising edge in this example)
Data on RX
(from slave)
t
SETUP
= t
HOLD
1/16bit time
t
SETUP
t
HOLD