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Depending on the update request source is configured in the TIMx_CTRL1.UPRS. When an update event occurs,
TIMx_STS.UDITF is set, all registers are updated:
Update auto-reload shadow registers with preload value(TIMx_AR), when TIMx_CTRL1.ARPEN = 1.
The prescaler shadow register is reloaded with the preload value(TIMx_PSC).
To avoid updating the shadow registers when new values are written to the preload registers, you can disable the
update by setting TIMx_CTRL1.UPDIS=1.
When an update event occurs, the counter will still be cleared and the prescaler counter will also be set to 0 (but the
prescaler value will remain unchanged).
The figure below shows some examples of the counter behavior and the update flags for different division factors in
the up-counting mode.