Nations Technologies Inc.
Tel
:
+86-755-86309900
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Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
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avoid CPU access to SRAM and prevent SRAM timing problems.
Additional steps can be taken to further reduce power consumption:
Adjust the LPR output to meet different power or frequency requirements;
Turn on or off the digital peripheral clock according to actual needs;
Turn off unnecessary analog peripherals;
If FLASH is not used, in order to further reduce power consumption, user can configure FLASH_AC.SLMEN
= 1 to put FLASH into sleep mode. Configuring FLASH_AC.SLMEN = 0 will restore the current state of
FLASH.
It should be noted that LP RUN can switch to LP SLEEP mode, STOP2 mode, STANDBY mode and RUN mode,
and can also return from LP SLEEP or STOP2. A system reset also exits LP RUN to RUN mode.
Exit LOW POWER RUN mode
The LOW POWER RUN mode can be exited by the following steps:
Clear PWR_CTRL1.LPREN and wait until PWR_STS2.LPRUNF is set to 1;
Set the FLASH read delay to greater than 2;
Clear FLASH_AC.LVMEN and ensure that the FLASH low voltage mode is canceled by polling the
FLASH_AC.LVMF bit;
Restore the system clock to the required state;
Configure the FLASH read cycle according to the system clock, and ensure that the read wait time is greater
than or equal to 20ns (for example, <50MHz, it can be configured to 0).
LOW POWER SLEEP mode
In LOW POWER SLEEP mode, all I/O pins remain in the same state as in RUN mode.
Enter LOW POWER SLEEP mode
To enter LOW POWER SLEEP mode, first need to enter LOW POWER RUN mode, and then enter SLEEP mode.
The specific steps to enter LOW POWER RUN mode and SLEEP mode are described in Section 3.2.3.1 and Section
Exit LOW POWER SLEEP mode
Exiting LOW POWER SLEEP mode is the same as exiting SLEEP mode, any interrupt or event can wake the device
from LOW POWER SLEEP mode. For details, see Section 3.2.2.2. It should be noted that the chip will return to
LOW POWER RUN mode after waking up from LOW POWER SLEEP mode.
STOP2 mode
STOP2 mode is based on Cortex
®
-M4F deep sleep mode, all core digital logic areas are powered off. Main voltage
regulator (MR) off, HSE/HSI/PLL off, MSI/LSE/LSI optional operation. CPU registers, 80-byte backup registers,