Lake Shore Model 340 Temperature Controller User’s Manual
Remote Operation
9-3
9.1.3 Status
Registers
There are two status registers. The Status Byte Register is described in Paragraph 9.1.3.1. The Standard
Event Status Register is described in Paragraph 9.1.3.2.
9.1.3.1
Status Byte Register and Service Request Enable Register
The Status Byte Register consists of a single byte of data containing six bits of information about the condition
of the Model 340.
STATUS BYTE REGISTER FORMAT
Bit
–
7 6 5 4 3 2 1 0
Weighting
–
128
64 32 16 8 4 2 1
Bit Name –
Ramp
Done
SRQ ESB Error Alarm
Settle New
OPT
New
A&B
If the Service Request is enabled, any of these bits being set causes the Model 340 to pull the SRQ
management low to signal the BUS CONTROLLER. These bits are reset to zero upon a serial poll of the
Status Byte Register. These reports can be inhibited by turning their corresponding bits in the Service
Request Enable Register to off.
The Service Request Enable Register allows the user to inhibit or enable any of the status reports in the
Status Byte Register. The
Q
SRE command is used to set the bits. If a bit in the Service Request Enable
Register is set (1), then that function is enabled. Also refer to the
Q
SRE command.
Ramp Done, Bit (7)
– This bit is set when the ramp is completed.
Service Request (SRQ) Bit (6)
– Determines whether the Model 340 is to report via the SRQ line and four
bits determine which status reports to make. If bits 0, 1, 2, 4 or 5 are set, then the corresponding bit in the
Status Byte Register is set. The Model 340 produces a service request only if bit 6 of the Service Request
Enable Register is set. If disabled, the Status Byte Register can still be read by the BUS CONTROLLER
by means of a serial poll (SPE) to examine the status reports, but the BUS CONTROLLER will not be
interrupted by the Service Request. The
Q
STB common command reads the Status Byte Register but will
not clear the bits. It must be understood that certain bits in the Status Byte Register are continually
changing.
Standard Event Status (ESB) Bit (5)
– When bit 5 is set, it indicates if one of the bits from the Standard
Event Status Register has been set. (Refer to Paragraph 9.1.3.2.)
Error, Bit (4)
– This bit is set when there is an instrument error not related to the bus.
Alarm, Bit (3)
– This bit is set when there is an alarm condition.
Settle, Bit (2)
– This bit is set when the settle conditions have been reached.
New OPT, Bit (1)
– New data is available from the optional inputs.
New A&B, Bit (0)
– New data is available from the two normal inputs.
9.1.3.2
Standard Event Status Register and Standard Event Status Enable Register
The Standard Event Status Register supplies various conditions of the Model 340.
STANDARD EVENT STATUS REGISTER FORMAT
Bit
–
7 6 5 4 3 2 1 0
Weighting
–
128
64 32 16 8 4 2 1
Bit Name –
PON
Not Used
CME EXE DDE QYE
Not Used
OPC
Bits 1 and 6 are not used. The user is only interrupted with the reports of this register if the bits have been
enabled in the Standard Event Status Enable Register and if bit 5 of the Service Request Enable Register
has been set.