Juniper JUNOSE 10.0.X PHYSICAL LAYER, Руководство по настройке

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Framing type, clock source, and the cable length for each controller
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Framing type, line code, and clock source for each channel
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Timeslot mapping and line speed for each fractional channel
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HDLC channel information, such as data inversion information, CRC type, idle
character, MTU, and MRU
Configuration Tasks
The following sections describe how to configure the layers on cOCx/STMx interfaces.
SONET/SDH Configuration Tasks
To configure SONET/SDH on a cOCx/STMx interface:
1.
Select an interface.
2.
Specify a clock source for the interface.
3.
Specify that the mode be SDH, or accept the default mode, SONET.
4.
(Optional) Assign a text description or an alias to the interface.
5.
(Optional) Disable processing of SNMP link status information for the section
and line layers of the interface.
6.
Configure the path for the interface.
7.
(Optional—not recommended) Overwrite the automatic setting for the path signal
label (C2) byte.
8.
(Optional) Enable processing of SNMP link status information for the path layer
of the interface.
9.
(Optional) Configure the router to use remote defect indications (RDIs) at the
path layer to determine the operational status of a path.
10.
(MPLS fast reroute over SONET/SDH interfaces) Specify the time duration after
which the router sets an alarm when it records a defect at the path layer.
11.
(MPLS fast reroute over SONET/SDH interfaces) Specify the time duration after
which the router sets an alarm when it records a defect at the line or section
layer.
12.
Configure APS/MSP for the interface.
For information about configuring APS/MSP, see “Configuring APS/MSP” on page
89 in “Configuring Unchannelized OCx/STMx Interfaces” on page 73.
You must now configure the next layer on the interface: E1, T1, or E3. See “T1/E1
Configuration Tasks” on page 124 or “T3 Configuration Tasks” on page 130.
clock source
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Use to configure the transmit clock source for the interface.
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For production networks, configure all STMx ports on the line module for internal
chassis timing. You must also ensure that the chassis reference clock is of good
Configuration Tasks
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Chapter 4: Configuring Channelized OCx/STMx Interfaces