Hitachi H8S/2645, Руководство по оборудованию

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Exception handling state
Bus-released state
Hardware standby mode
* 2
Software standby mode
Reset state
* 1
Sleep mode
Power-down state
*
3
Program execution state
End of bus request
Bus request
Inte
rru
pt re
qu
est
External interrupt request
RES= High
Request for exception handling
STBY= High, RES= Low
En
d o
f b
us
req
ue
st
Bus request
SLEEP
instruction
with
SSBY = 0
SLEEP
instruction
with
SSBY = 1
Notes: * 1
*
2
* 3
From any state except hardware standby mode, a transition to the reset state occurs whenever
RES
goes low. A transition can also be made to the reset state when the
watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when
STBY
goes low.
Apart from these states, there are also the watch mode, subactive mode, and the subsleep mode.
See section 22, Power-Down Modes.
End of exception
handling
Figure 2-15 State Transitions
2.8.2 Reset State
When the
RES
goes low, all current processing stops and the CPU enters the reset state. In reset
state all interrupts are disenabled.
Reset exception handling starts when the
RES
signal changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 12,
Watchdog Timer.