Hitachi H8S/2645, Руководство по оборудованию

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Section 21 Clock Pulse Generator
21.1 Overview
The H8S/2646 Series has a built-in clock pulse generator (CPG) that generates the system clock
(ø), the bus master clock, and internal clocks.
The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, clock
selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock
oscillator, and waveform shaping circuit. The frequency can be changed by means of the PLL
circuit in the CPG. Frequency changes are performed by software by means of settings in the
system clock control register (SCKCR) and low-power control register (LPWRCR).
21.1.1 Block Diagram
Figure 21-1 shows a block diagram of the clock pulse generator.
Legend:
LPWRCR:
SCKCR:
Low-power control register
System clock control register
EXTAL
XTAL
PLL circuit
(
×
1,
×
2,
×
4)
Medium-
speed
clock divider
System
clock
oscillator
Clock
selection
circuit
ø SUB
WDT1 count clock
System clock
to ø pin
Internal clock to
supporting modules
Bus master clock
to CPU and DTC
ø/2 to
ø/32
ø
SCK2 to SCK0
SCKCR
STC1, STC0
OSC1
OSC2
Waveform
Generation
Circuit
Subclock
oscillator
LPWRCR
Bus
master
clock
selection
circuit
Figure 21-1 Block Diagram of Clock Pulse Generator