Hitachi H8S/2645, Руководство по оборудованию

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1010
TCR0—Timer Control Register 0 H'FF10 TPU0
7
CCLR2
0
R/W
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
0
TPSC0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
Bit
Initial value
Read/Write
Time Prescaler
0 Internal clock: counts on ø/1
Internal clock: counts on ø/4
Internal clock: counts on ø/16
Internal clock: counts on ø/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
External clock: counts on TCLKD pin input
0
1
0
1
0
1
1 0
1
0
1
0
1
Counter Clear
0 TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
*
1
TCNT clearing disabled
TCNT cleared by TGRC compare match/input capture
* 2
TCNT cleared by TGRD compare match/input capture
*
2
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
* 1
0
1
0
1
0
1
1 0
1
0
1
0
1
Notes: * 1
*
2
Synchronous operation setting is performed by setting the
SYNC bit in TSYR to 1.
When TGRC or TGRD is used as a buffer register, TCNT is
not cleared because the buffer register setting has priority,
and compare match/input capture does not occur.
Clock Edge
0
1
Count at rising edge
Count at falling edge
Count at both edges
0
1
—
Note: Internal clock edge selection is valid when the input clock
is ø/4 or slower. This setting is ignored if the input clock is ø/1,
or when overflow/underflow of another channel is selected.