Hitachi H8S/2645, Руководство по оборудованию

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108
5.2.5 IRQ Status Register (ISR)
7
—
0
R/(W)
*
6
—
0
R/(W)
*
5
IRQ5F
0
R/(W)
*
4
IRQ4F
0
R/(W)
*
3
IRQ3F
0
R/(W)
*
0
IRQ0F
0
R/(W)
*
2
IRQ2F
0
R/(W)
*
1
IRQ1F
0
R/(W)
*
Bit
Initial value
R/W
Note: * Only 0 can be written, to clear the flag.
:
:
:
ISR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt
requests.
ISR is initialized to H'00 by a reset and in hardware standby mode.
They are not initialized in software standby mode.
Bits 7 and 6—Reserved: These bits are always read as 0.
Bits 5 to 0—IRQ5 to IRQ0 flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ5 to
IRQ0 interrupt requests.
Bit n
IRQnF Description
0 [Clearing conditions] (Initial value)
•
Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag
•
When interrupt exception handling is executed when low-level detection is set
(IRQnSCB = IRQnSCA = 0) and
IRQn
input is high
•
When IRQn interrupt exception handling is executed when falling, rising, or both-edge
detection is set (IRQnSCB = 1 or IRQnSCA = 1)
•
When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the
DTC is cleared to 0
1 [Setting conditions]
•
When
IRQn
input goes low when low-level detection is set (IRQnSCB = IRQnSCA =
0)
•
When a falling edge occurs in
IRQn
input when falling edge detection is set
(IRQnSCB = 0, IRQnSCA = 1)
•
When a rising edge occurs in
IRQn
input when rising edge detection is set
(IRQnSCB = 1, IRQnSCA = 0)
•
When a falling or rising edge occurs in
IRQn
input when both-edge detection is set
(IRQnSCB = IRQnSCA = 1)
(n = 5 to 0)