Hitachi H8S/2645, Руководство по оборудованию

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9.11.2 Register Configuration
Table 9-22 shows the port D register configuration.
Table 9-22 Port D Registers
Name Abbreviation R/W Initial Value Address
*
Port D data direction register PDDDR W H'00 H'FE3C
Port D data register PDDR R/W H'00 H'FF0C
Port D register PORTD R Undefined H'FFBC
Port D MOS pull-up control register PDPCR R/W H'00 H'FE43
Note: * Lower 16 bits of the address.
Port D Data Direction Register (PDDDR)
Bit : 7 6 5 4 3 2 1 0
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
Initial value : 0 0 0 0 0 0 0 0
R/W : W W W W W W W W
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.
PDDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Port D Data Register (PDDR)
Bit : 7 6 5 4 3 2 1 0
PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to
PD0).
PDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.