Section
Page
Description
B.2 Functions
882
TXACK—Transmit Acknowledge Register H'F80A HCAN
15
TXACK7
0
R/(W)
*
14
TXACK6
0
R/(W)
*
13
TXACK5
0
R/(W)
*
12
TXACK4
0
R/(W)
*
11
TXACK3
0
R/(W)
*
8
—
0
—
10
TXACK2
0
R/(W)
*
9
TXACK1
0
R/(W)
*
7
TXACK15
0
R/(W)
*
6
TXACK14
0
R/(W)
*
5
TXACK13
0
R/(W)
*
4
TXACK12
0
R/(W)
*
3
TXACK11
0
R/(W)
*
0
TXACK8
0
R/(W)
*
2
TXACK10
0
R/(W)
*
1
TXACK9
0
R/(W)
*
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Note added
Note:
*
Only 1 can be written, to clear the flag.
883
ABACK—Abort Acknowledge Register
H'F80C
HCAN
15
ABACK7
0
R/(W)
*
14
ABACK6
0
R/(W)
*
13
ABACK5
0
R/(W)
*
12
ABACK4
0
R/(W)
*
11
ABACK3
0
R/(W)
*
8
—
0
—
10
ABACK2
0
R/(W)
*
9
ABACK1
0
R/(W)
*
7
ABACK15
0
R/(W)
*
6
ABACK14
0
R/(W)
*
5
ABACK13
0
R/(W)
*
4
ABACK12
0
R/(W)
*
3
ABACK11
0
R/(W)
*
0
ABACK8
0
R/(W)
*
2
ABACK10
0
R/(W)
*
1
ABACK9
0
R/(W)
*
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Note added
Note:
*
Only 1 can be written, to clear the flag.
RXPR—Receive Complete Register
H'F80E
HCAN
15
RXPR7
0
R/(W)
*
14
RXPR6
0
R/(W)
*
13
RXPR5
0
R/(W)
*
12
RXPR4
0
R/(W)
*
11
RXPR3
0
R/(W)
*
8
RXPR0
0
R/(W)
*
10
RXPR2
0
R/(W)
*
9
RXPR1
0
R/(W)
*
7
RXPR15
0
R/(W)
*
6
RXPR14
0
R/(W)
*
5
RXPR13
0
R/(W)
*
4
RXPR12
0
R/(W)
*
3
RXPR11
0
R/(W)
*
0
RXPR8
0
R/(W)
*
2
RXPR10
0
R/(W)
*
1
RXPR9
0
R/(W)
*
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Note added
Note:
*
Only 1 can be written, to clear the flag.
Содержание H8S/2645
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Страница 120: ...88 ...
Страница 132: ...100 ...
Страница 160: ...128 ...
Страница 172: ...140 ...
Страница 235: ...203 Transfer SAR or DAR DAR or SAR Block area First block Nth block Figure 8 8 Memory Mapping in Block Transfer Mode ...
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Страница 444: ...412 ...
Страница 530: ...498 ...
Страница 562: ...530 ...
Страница 642: ...610 ...
Страница 662: ...630 ...
Страница 688: ...656 ...
Страница 756: ...724 ...
Страница 784: ...752 ...
Страница 812: ...780 ...
Страница 837: ...805 A 2 Instruction Codes Table A 2 shows the instruction codes ...
Страница 1152: ...1120 ...