Hitachi H8S/2645, Руководство по оборудованию, Страница: 24 / 1153

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10.4.3 Synchronous Operation ........................................................................................ 345
10.4.4 Buffer Operation ................................................................................................... 347
10.4.5 Cascaded Operation .............................................................................................. 351
10.4.6 PWM Modes ......................................................................................................... 353
10.4.7 Phase Counting Mode ........................................................................................... 358
10.5 Interrupts ............................................................................................................................ 365
10.5.1 Interrupt Sources and Priorities ............................................................................ 365
10.5.2 DTC Activation .................................................................................................... 367
10.5.3 A/D Converter Activation..................................................................................... 367
10.6 Operation Timing ............................................................................................................... 368
10.6.1 Input/Output Timing ............................................................................................. 368
10.6.2 Interrupt Signal Timing ........................................................................................ 372
10.7 Usage Notes ....................................................................................................................... 376
Section 11 Programmable Pulse Generator (PPG) ............................................387
11.1 Overview............................................................................................................................ 387
11.1.1 Features ................................................................................................................. 387
11.1.2 Block Diagram...................................................................................................... 388
11.1.3 Pin Configuration.................................................................................................. 389
11.1.4 Registers................................................................................................................ 390
11.2 Register Descriptions ......................................................................................................... 391
11.2.1 Next Data Enable Registers H and L (NDERH, NDERL) ................................... 391
11.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 392
11.2.3 Next Data Registers H and L (NDRH, NDRL) .................................................... 393
11.2.4 Notes on NDR Access .......................................................................................... 393
11.2.5 PPG Output Control Register (PCR) .................................................................... 395
11.2.6 PPG Output Mode Register (PMR) ...................................................................... 397
11.2.7 Port 1 Data Direction Register (P1DDR).............................................................. 400
11.2.8 Module Stop Control Register A (MSTPCRA).................................................... 400
11.3 Operation............................................................................................................................ 401
11.3.1 Overview............................................................................................................... 401
11.3.2 Output Timing ...................................................................................................... 402
11.3.3 Normal Pulse Output ............................................................................................ 403
11.3.4 Non-Overlapping Pulse Output ............................................................................ 405
11.3.5 Inverted Pulse Output ........................................................................................... 408
11.3.6 Pulse Output Triggered by Input Capture............................................................. 409
11.4 Usage Notes .......................................................................................................................... 410
Section 12 Watchdog Timer ..............................................................................413
12.1 Overview............................................................................................................................ 413
12.1.1 Features ................................................................................................................. 413
12.1.2 Block Diagram...................................................................................................... 414
12.1.3 Pin Configuration.................................................................................................. 416