737
22.2.5
Module Stop Control Register (MSTPCR)
MSTPCRA
Bit
:
7
6
5
4
3
2
1
0
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value :
0
0
1
1
1
1
1
1
R/W
:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRB (H8S/2646, H8S/2646R, H8S/2645)
Bit
:
7
6
5
4
3
2
1
0
MSTPB7 MSTPB6
—
MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0
Initial value :
1
1
1
1
1
1
1
1
R/W
:
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
MSTPCRB (H8S/2648, H8S/2648R, H8S/2647)
Bit
:
7
6
5
4
3
2
1
0
MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0
Initial value :
1
1
1
1
1
1
1
1
R/W
:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRC
Bit
:
7
6
5
4
3
2
1
0
MSTPC7
—
MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
Initial value :
1
1
1
1
1
1
1
1
R/W
:
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRD
Bit
:
7
6
5
4
3
2
1
0
MSTPD7 MSTPD6
—
—
—
—
—
—
Initial value :
1
1
Undefined Undefined Undefined Undefined Undefined Undefined
R/W
:
R/W
R/W
—
—
—
—
—
—
MSTPCR, comprising four 8-bit readable/writable registers, performs module stop mode control.
MSTPCRA to MSTPCRC are initialized to H'3FFFFF by a reset and in hardware standby mode.
MSTPCRD is initialized to B'11****** by a reset and in hardware standby mode. They are not
initialized in software standby mode.
Содержание H8S/2645
Страница 4: ......
Страница 16: ......
Страница 58: ...26 ...
Страница 110: ...78 ...
Страница 120: ...88 ...
Страница 132: ...100 ...
Страница 160: ...128 ...
Страница 172: ...140 ...
Страница 235: ...203 Transfer SAR or DAR DAR or SAR Block area First block Nth block Figure 8 8 Memory Mapping in Block Transfer Mode ...
Страница 418: ...386 ...
Страница 444: ...412 ...
Страница 530: ...498 ...
Страница 562: ...530 ...
Страница 642: ...610 ...
Страница 662: ...630 ...
Страница 688: ...656 ...
Страница 756: ...724 ...
Страница 784: ...752 ...
Страница 812: ...780 ...
Страница 837: ...805 A 2 Instruction Codes Table A 2 shows the instruction codes ...
Страница 1152: ...1120 ...